专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08996967B2 Rendering data write errors detectable 有权
标题翻译：呈现数据写错误可检测
公开(公告)号：US08996967B2
公开(公告)日：2015-03-31
申请号：US12852368
申请日：2010-08-06
申请人： Mustafa N. Kaynak , Alessandro Risso , Patrick R. Khayat
发明人： Mustafa N. Kaynak , Alessandro Risso , Patrick R. Khayat
IPC分类号： G06F11/00 , H03M13/29 , G11B20/10 , G11B20/18 , H03M13/00 , H03M13/09 , H03M13/19
CPC分类号： H03M13/2915 , G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10064 , G11B20/10074 , G11B20/10175 , G11B20/10194 , G11B20/10222 , G11B20/10296 , G11B20/10379 , G11B20/1833 , G11B2020/1853 , G11B2020/1863 , G11B2220/2516 , H03M13/098 , H03M13/13 , H03M13/19 , H03M13/2918 , H03M13/2927 , H03M13/293 , H03M13/6343
摘要： An embodiment of a data write path includes encoder and write circuits. The encoder circuit is configured to code data so as to render detectable a write error that occurs during a writing of the coded data to a storage medium, and the write circuit is configured to write the coded data to the storage medium. For example, such an embodiment may allow rendering detectable a write error that occurs while writing data to a bit-patterned storage medium.
摘要翻译：数据写入路径的实施例包括编码器和写入电路。编码器电路被配置为对数据进行编码，以便可读取在将编码数据写入存储介质期间发生的写错误，并且写电路被配置为将编码数据写入存储介质。例如，这样的实施例可以允许可读出在将数据写入位图案存储介质时发生的写入错误。

2. 发明授权

US08745466B2 Detecting data-write errors 有权
标题翻译：检测数据写错误
公开(公告)号：US08745466B2
公开(公告)日：2014-06-03
申请号：US12852397
申请日：2010-08-06
申请人： Mustafa N. Kaynak , Alessandro Risso , Patrick R. Khayat
发明人： Mustafa N. Kaynak , Alessandro Risso , Patrick R. Khayat
IPC分类号： G11C29/00
CPC分类号： H03M13/13 , G11B20/10064 , G11B20/10074 , G11B20/10175 , G11B20/10277 , G11B20/10296 , G11B20/1833 , G11B2220/252 , H03M13/451 , H03M13/458
摘要： An embodiment of a data read path includes recovery and decoder circuits. The recovery circuit is operable to recover coded data from a storage medium, and the decoder circuit is operable to detect, in the recovered data, a write error that occurred during a writing of the coded data to the storage medium. For example, such an embodiment may allow detection of a write error that occurred while writing data to a bit-patterned storage medium.
摘要翻译：数据读取路径的实施例包括恢复和解码器电路。恢复电路可操作以从存储介质中恢复编码数据，并且解码器电路可操作以在恢复的数据中检测在将编码数据写入存储介质期间发生的写入错误。例如，这样的实施例可以允许检测在将数据写入位图案的存储介质时发生的写入错误。

3. 发明申请

US20110075287A1 System and method for map detector for symbol based error correction codes 有权
标题翻译：用于基于符号的纠错码的地图检测器的系统和方法
公开(公告)号：US20110075287A1
公开(公告)日：2011-03-31
申请号：US12653615
申请日：2009-12-16
申请人： Alessandro Risso , Mustafa N. Kaynak , Patrick Khayat
发明人： Alessandro Risso , Mustafa N. Kaynak , Patrick Khayat
IPC分类号： G11B27/36 , H03M13/00 , H03M13/41
CPC分类号： H03M13/1171 , H03M13/2957 , H03M13/3905 , H03M13/4146 , H03M13/6331 , H03M13/6343
摘要： A system for decoding data includes a symbol based error correction code device. The error correction code device includes a channel detector configured to generate probability mass function (PMF) information. The error correction code device further includes a decoder coupled to the channel detector. The decoder is configured to use the PMF information from the channel detector to perform an error correction code operation. The decoder also is configured to generate PMF information. The channel detector is configured to receive extrinsic PMF information in a turbo equalization scheme.
摘要翻译：用于解码数据的系统包括基于符号的纠错码装置。误差校正码装置包括被配置为产生概率质量函数（PMF）信息的信道检测器。纠错码装置还包括耦合到信道检测器的解码器。解码器被配置为使用来自信道检测器的PMF信息来执行纠错码操作。解码器还被配置为生成PMF信息。信道检测器被配置为在turbo均衡方案中接收外部PMF信息。

4. 发明申请

US20110080668A1 CLOSELY COUPLED VECTOR SEQUENCERS FOR A READ CHANNEL PIPELINE 有权
标题翻译：用于读通道管道的闭合耦合矢量序列
公开(公告)号：US20110080668A1
公开(公告)日：2011-04-07
申请号：US12896609
申请日：2010-10-01
申请人： Sivagnanam Parthasarathy , Alessandro Risso , Dillip Dash
发明人： Sivagnanam Parthasarathy , Alessandro Risso , Dillip Dash
IPC分类号： G11B5/09
CPC分类号： G11B5/09 , G11B20/10009 , G11B20/10027 , G11B20/10296 , G11B2220/2516
摘要： A system and method involving a read channel pipeline having a plurality of vector sequencers that may be used to control the processing blocks. In one embodiment, a read channel pipeline may include processing blocks that may be controlled a command word provided by vector sequencers. Incoming data may be delineated by identifying an early period, a steady-state period, and a trailing period. Instead of controlling these blocks with a static state machine controller, a plurality of vector sequencers are coupled to the plurality of processing blocks. Thus, a first vector sequencer may control the processing blocks during the early period and the steady state period, but then hand off control to a second vector sequencer for the trailing period. Using vector sequencers for implementing command words allows for greater programming flexibility once the device has been manufactured and deployed for use.
摘要翻译：一种涉及具有可用于控制处理块的多个向量定序器的读通道流水线的系统和方法。在一个实施例中，读通道流水线可以包括可以被控制由矢量定序器提供的命令字的处理块。可以通过识别早期，稳定状态时段和尾随时段来描绘输入数据。代替使用静态机器控制器控制这些块，多个向量定序器被耦合到多个处理块。因此，第一矢量定序器可以在早期和稳定状态时段期间控制处理块，但是在后续周期中切换到第二矢量定序器的控制。使用矢量顺控程序来实现命令字可以在设备制造和部署使用后实现更大的编程灵活性。

5. 发明申请

US20050138535A1 Method and system for branch metric calculation in a viterbi decoder 审中-公开
标题翻译：维特比解码器中分支度量计算的方法和系统
公开(公告)号：US20050138535A1
公开(公告)日：2005-06-23
申请号：US10727063
申请日：2003-12-02
申请人： Sivagnanam Parthasarathy , Alessandro Risso
发明人： Sivagnanam Parthasarathy , Alessandro Risso
IPC分类号： H03M13/41 , G06K5/04 , G11B5/00 , G11B20/20 , H03M13/03
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/41 , H03M13/4169
摘要： In a convolutional decoder, eight branch labels for branches in two trellis butterflies are calculated using a single output of an encoder. For a group of four consecutive states, Si, Si+1, Si+2, and Si+3, state Si+3 is loaded into a convolutional encoder and the convolutional encoder input bit is set to 1. The output bits of the convolutional encoder are used as a branch label in a first trellis butterfly. A branch label in the second trellis butterfly is calculated with a formula in a branch label calculator using the convolutional encoder output bits as an input to the formula. The remaining branch labels are calculated from the convolutional encoder output and the branch label output from the branch label calculator. Selected bits of the branch labels are used to address a small branch metric register file.
摘要翻译：在卷积解码器中，使用编码器的单个输出来计算两个网格蝴蝶中的分支的八个分支标签。对于四个连续状态的组，分别是S i，I i，I i，S i，I i，状态S i + 3 +被加载到卷积编码器中，并且卷积编码器输入比特被设置为1.卷积编码器的输出比特用作第一格子蝴蝶使用卷积编码器输出比特作为公式的输入，在分支标签计算器中用公式计算第二格状蝴蝶中的分支标签。剩余的分支标签是从卷积编码器输出和从分支标签计算器输出的分支标签计算的。分支标签的选定位用于寻址小分支度量寄存器文件。

6. 发明授权

US08694877B2 Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method 有权
标题翻译：最大对数映射等价对数似然比生成软维特比架构系统和方法
公开(公告)号：US08694877B2
公开(公告)日：2014-04-08
申请号：US12924707
申请日：2010-10-01
申请人： Sivagnanam Parthasarathy , Lun Bin Huang , Alessandro Risso
发明人： Sivagnanam Parthasarathy , Lun Bin Huang , Alessandro Risso
IPC分类号： H03M13/03
CPC分类号： H03M13/4146 , G06F11/1076 , G11B20/18 , H03M13/3905 , H03M13/3927 , H03M13/4184 , H03M13/42 , H03M13/6343 , H03M13/6502 , H04L1/0054 , H04L1/0055
摘要： A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.
摘要翻译：修改的软输出维特比算法（SOVA）检测器接收软信息值序列，并为每个软信息值确定最佳路径和备用路径，并且进一步确定当给定软件的最佳和替代路径导致相同值时信息值，是否存在离开替代路径的第三路径，其导致相对于给定软信息值的最佳路径的相反决定。然后，SOVA检测器在更新最佳路径的可靠性时考虑第三条路径。改进的SOVA检测器通过Fossorier方法有效地实现了最大对数映射的等效性，并且包括SOVA检测器的前N个级的修正的可靠性度量单位，其中N是给定路径的存储器深度，并且包括用于检测器的剩余阶段。

7. 发明授权

US07290081B2 Apparatus and method for implementing a ROM patch using a lockable cache 有权
标题翻译：使用可锁定缓存实现ROM补丁的装置和方法
公开(公告)号：US07290081B2
公开(公告)日：2007-10-30
申请号：US10146537
申请日：2002-05-14
申请人： Sivagnanam Parthasarathy , Alessandro Risso
发明人： Sivagnanam Parthasarathy , Alessandro Risso
IPC分类号： G06F12/00
CPC分类号： G06F9/328 , G06F8/66 , G06F9/3004 , G06F9/30087 , G06F12/126
摘要： A ROM patching apparatus for use in a data processing system that executes instruction code stored in the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first replacement cache line containing a first new instruction suitable for replacing at least a portion of the code in the ROM; 2) a lockable cache; 3) core processor logic operable to read from an associated memory a patch table containing a first table entry, the first table entry containing 1) the first new instruction and 2) a first patch address identifying a first patched ROM address of the at least a portion of the code in the ROM. The core processor logic loads the first new instruction from the patch table into the patch buffer, stores the first replacement cache line from the patch buffer into the lockable cache, and locks the first replacement cache line into the lockable cache.
摘要翻译：一种用于执行存储在ROM中的指令代码的数据处理系统中的ROM修补装置。 ROM修补装置包括：1）补丁缓冲器，用于存储包含适于替换ROM中的代码的至少一部分的第一新指令的第一替换高速缓存行; 2）可锁定缓存; 3）核心处理器逻辑，可操作以从相关联的存储器读取包含第一表项的修补表，所述第一表条目包含1）所述第一新指令;以及2）第一补丁地址，其标识所述至少一个部分ROM中的代码。核心处理器逻辑将补丁表中的第一个新指令加载到补丁缓冲区中，将补丁缓冲区中的第一个替换高速缓存行存储到可锁定高速缓存中，并将第一个替换高速缓存行锁定到可锁定高速缓存中。

8. 发明授权

US08510642B2 System and method for map detector for symbol based error correction codes 有权
标题翻译：用于基于符号的纠错码的地图检测器的系统和方法
公开(公告)号：US08510642B2
公开(公告)日：2013-08-13
申请号：US12653615
申请日：2009-12-16
申请人： Alessandro Risso , Mustafa N. Kaynak , Patrick Khayat
发明人： Alessandro Risso , Mustafa N. Kaynak , Patrick Khayat
IPC分类号： H03M13/03
CPC分类号： H03M13/1171 , H03M13/2957 , H03M13/3905 , H03M13/4146 , H03M13/6331 , H03M13/6343
摘要： A system for decoding data includes a symbol based error correction code device. The error correction code device includes a channel detector configured to generate probability mass function (PMF) information. The error correction code device further includes a decoder coupled to the channel detector. The decoder is configured to use the PMF information from the channel detector to perform an error correction code operation. The decoder also is configured to generate PMF information. The channel detector is configured to receive extrinsic PMF information in a turbo equalization scheme.
摘要翻译：用于解码数据的系统包括基于符号的纠错码装置。误差校正码装置包括被配置为产生概率质量函数（PMF）信息的信道检测器。纠错码装置还包括耦合到信道检测器的解码器。解码器被配置为使用来自信道检测器的PMF信息来执行纠错码操作。解码器还被配置为生成PMF信息。信道检测器被配置为在turbo均衡方案中接收外部PMF信息。

9. 发明授权

US08379339B2 Closely coupled vector sequencers for a read channel pipeline 有权
标题翻译：用于读通道管道的紧耦合矢量定序器
公开(公告)号：US08379339B2
公开(公告)日：2013-02-19
申请号：US12896609
申请日：2010-10-01
申请人： Sivagnanam Parthasarathy , Alessandro Risso , Dillip Dash
发明人： Sivagnanam Parthasarathy , Alessandro Risso , Dillip Dash
IPC分类号： G11B5/09
CPC分类号： G11B5/09 , G11B20/10009 , G11B20/10027 , G11B20/10296 , G11B2220/2516
摘要： A system and method involving a read channel pipeline having a plurality of vector sequencers that may be used to control the processing blocks. In one embodiment, a read channel pipeline may include processing blocks that may be controlled a command word provided by vector sequencers. Incoming data may be delineated by identifying an early period, a steady-state period, and a trailing period. Instead of controlling these blocks with a static state machine controller, a plurality of vector sequencers are coupled to the plurality of processing blocks. Thus, a first vector sequencer may control the processing blocks during the early period and the steady state period, but then hand off control to a second vector sequencer for the trailing period. Using vector sequencers for implementing command words allows for greater programming flexibility once the device has been manufactured and deployed for use.
摘要翻译：一种涉及具有可用于控制处理块的多个向量定序器的读通道流水线的系统和方法。在一个实施例中，读通道流水线可以包括可以被控制由矢量定序器提供的命令字的处理块。可以通过识别早期，稳定状态时段和尾随时段来描绘输入数据。代替使用静态机器控制器控制这些块，多个向量定序器被耦合到多个处理块。因此，第一矢量定序器可以在早期和稳定状态时段期间控制处理块，但是在后续周期中切换到第二矢量定序器的控制。使用矢量顺控程序来实现命令字可以在设备制造和部署使用后实现更大的编程灵活性。

10. 发明申请

US20120036414A1 RENDERING DATA WRITE ERRORS DETECTABLE 有权
标题翻译：渲染数据写入错误检测
公开(公告)号：US20120036414A1
公开(公告)日：2012-02-09
申请号：US12852368
申请日：2010-08-06
申请人： Mustafa N. KAYNAK , Alessandro RISSO , Patrick R. KHAYAT
发明人： Mustafa N. KAYNAK , Alessandro RISSO , Patrick R. KHAYAT
IPC分类号： H03M13/05 , H03M13/19 , G06F11/10 , H03M13/09
CPC分类号： H03M13/2915 , G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10064 , G11B20/10074 , G11B20/10175 , G11B20/10194 , G11B20/10222 , G11B20/10296 , G11B20/10379 , G11B20/1833 , G11B2020/1853 , G11B2020/1863 , G11B2220/2516 , H03M13/098 , H03M13/13 , H03M13/19 , H03M13/2918 , H03M13/2927 , H03M13/293 , H03M13/6343
摘要： An embodiment of a data write path includes encoder and write circuits. The encoder circuit is operable to code data so as to render detectable a write error that occurs during a writing of the coded data to a storage medium, and the write circuit is operable to write the coded data to the storage medium. For example, such an embodiment may allow rendering detectable a write error that occurs while writing data to a bit-patterned storage medium.
摘要翻译：数据写入路径的实施例包括编码器和写入电路。编码器电路可操作以对数据进行编码，以便可读取在将编码数据写入存储介质期间发生的写错误，并且写电路可操作以将编码数据写入存储介质。例如，这样的实施例可以允许可读出在将数据写入位图案存储介质时发生的写入错误。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式