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1. 发明授权

US08767854B2 Modulation code set (MCS) and LDPC (low density parity check) coding within multiple user, multiple access, and/or MIMO wireless communications 有权
标题翻译：在多用户，多访问和/或MIMO无线通信中的调制码集（MCS）和LDPC（低密度奇偶校验）编码
公开(公告)号：US08767854B2
公开(公告)日：2014-07-01
申请号：US13221017
申请日：2011-08-30
申请人： Jun Zheng , Vinko Erceg , Andrew J. Blanksby
发明人： Jun Zheng , Vinko Erceg , Andrew J. Blanksby
IPC分类号： H04L5/12 , H04L23/02
CPC分类号： H04L27/2647 , H04L1/0003 , H04L1/0009 , H04L1/0041 , H04L1/0045 , H04L1/0057 , H04L1/0059 , H04L1/0065 , H04L1/0068 , H04L1/0071 , H04L1/0618 , H04L5/0057 , H04L27/2626
摘要： Modulation code set (MCS) and LDPC (Low Density Parity Check) coding within multiple user, multiple access, and/or MIMO wireless communications. Selective operation in accordance with different operational modes is performed. Operation within a first mode may correspond to that which is in full compliance with a given protocol, standard, and/or recommended practice, while operation within a second mode may correspond to that which provides additional/augmented capability and/or functionality with respect to that protocol, standard, and/or recommended practice. Operational modes selectivity may be made between proprietary and non-proprietary modes of operation. All available modulation coding sets (MCSs) may be in employed by providing such multi-mode operation. When operating within one of the operational modes (e.g., proprietary), a signal is generated to include an integer number of data bits per orthogonal frequency division multiplexing (OFDM) symbol using any desired operation (e.g., floor, ceiling, rounding, etc.).
摘要翻译：多用户，多路访问和/或MIMO无线通信中的调制码集（MCS）和LDPC（低密度奇偶校验）编码。执行根据不同操作模式的选择性操作。在第一模式中的操作可以对应于完全符合给定协议，标准和/或推荐做法的操作，而在第二模式中的操作可以对应于相对于提供附加/增强能力和/或功能的操作该协议，标准和/或推荐的做法。可以在专有和非专有操作模式之间进行操作模式选择。可以通过提供这种多模式操作来使用所有可用的调制编码集（MCS）。当在一种操作模式（例如，专有）中操作时，使用任何期望的操作（例如，地板，天花板，四舍五入等）生成信号以包括每个正交频分复用（OFDM）符号的整数个数据位。）。

2. 发明授权

US08683303B2 Operational parameter adaptable LDPC (low density parity check) decoder 有权
标题翻译：操作参数适应型LDPC（低密度奇偶校验）解码器
公开(公告)号：US08683303B2
公开(公告)日：2014-03-25
申请号：US13433524
申请日：2012-03-29
申请人： Andrew J. Blanksby
发明人： Andrew J. Blanksby
IPC分类号： H03M13/00
CPC分类号： H03M13/112 , H03M13/1117 , H03M13/1134 , H03M13/1137 , H03M13/658 , H03M13/6583 , H03M13/6588 , H03M13/6591
摘要： Operational parameter adaptable LDPC (Low Density Parity Check) decoder. A novel means is presented by which LDPC coded signal can be decoded, and any one or more operational parameters can be adjusted during the decoding processing. For example, the original information extracted from a received LDPC coded signal (e.g., log likelihood ratios (LLRs)), can be modified during (or before) the iterative decoding processing performed in accordance with decoding an LDPC coded signal. Such modification of an operational parameter can include any one or combination of scaling, compression (and expansion/decompression), adding an offset to or subtracting an offset from, scaling, rounding, and/or some other modification of an operational parameter. The bit (or variable) edge messages and/or the check edge messages can also undergo modification during decoding processing. In addition, the operational parameter modification can be selective, in that, different modification can be performed to different parameters and/or during different decoding iterations.
摘要翻译：操作参数适应型LDPC（低密度奇偶校验）解码器。提出了可以解码LDPC编码信号的新颖手段，并且可以在解码处理期间调整任何一个或多个操作参数。例如，可以根据对LDPC编码信号的解码执行的迭代解码处理（或之前）修改从接收的LDPC编码信号（例如对数似然比（LLR））提取的原始信息。操作参数的这种修改可以包括缩放，压缩（和扩展/解压缩），向偏移量增加偏移量，减少偏移量，缩放，舍入和/或操作参数的某些其他修改的任何一个或组合。位（或可变）边消息和/或校验边消息也可以在解码处理期间进行修改。此外，操作参数修改可以是选择性的，因为可以对不同的参数和/或在不同的解码迭代期间执行不同的修改。

3. 发明授权

US08433971B2 Communication device architecture for in-place constructed LDPC (low density parity check) code 有权
标题翻译：用于就地构造的LDPC（低密度奇偶校验）码的通信设备架构
公开(公告)号：US08433971B2
公开(公告)日：2013-04-30
申请号：US12770068
申请日：2010-04-29
申请人： Andrew J. Blanksby , Ba-Zhong Shen , Jason A. Trachewsky
发明人： Andrew J. Blanksby , Ba-Zhong Shen , Jason A. Trachewsky
IPC分类号： H03M13/00
CPC分类号： H03M13/1102 , H03M13/033 , H03M13/1134 , H03M13/1137 , H03M13/116 , H03M13/1185 , H03M13/1188 , H03M13/618 , H03M13/6362 , H03M13/6393 , H03M13/6502 , H03M13/6516 , H03M13/6527 , H04L1/005 , H04L1/0057
摘要： Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform encoding of respective information bit groups using more than one type of LDPC codes. A switching module can select any one of the LDPC codes within an in-place LDPC code for use by an LDPC encoder circuitry to generate an LDPC coded signal. Depending on which sub-matrices of a superimposed LDPC matrix are enabled or disabled, one of the LDPC matrices from within an in-place LDPC code matrix set may be selected. A corresponding, respective generator matrix may be generated from each respective LDPC matrix. Selection among the various LDPC codes may be in accordance with a predetermined sequence, of based operating conditions of the communication device or communication system.
摘要翻译：用于就地构造的LDPC（低密度奇偶校验）码的通信设备架构。具有相似特性的LDPC码的智能设计允许通信设备的非常有效的硬件实现，该通信设备可操作以使用多于一种类型的LDPC码执行各个信息位组的编码。交换模块可以在就地LDPC码内选择任何一个LDPC码，供LDPC编码器电路使用以产生LDPC编码信号。根据叠加的LDPC矩阵的哪些子矩阵被使能或禁用，可以选择来自就地内LDPC码矩阵集合的LDPC矩阵之一。可以从每个相应的LDPC矩阵生成相应的相应的生成器矩阵。各种LDPC码之间的选择可以与通信设备或通信系统的基于操作条件的预定顺序相一致。

4. 发明授权

US08341489B2 Permuted accelerated LDPC (Low Density Parity Check) decoder 有权
标题翻译：加密LDPC（低密度奇偶校验）解码器
公开(公告)号：US08341489B2
公开(公告)日：2012-12-25
申请号：US12512820
申请日：2009-07-30
申请人： Alvin Lai Lin , Andrew J. Blanksby
发明人： Alvin Lai Lin , Andrew J. Blanksby
IPC分类号： H03M13/00
CPC分类号： H03M13/13 , H03M13/1137 , H03M13/1145 , H03M13/116 , H04L1/005 , H04L1/0057
摘要： Permuted accelerated LDPC (Low Density Parity Check) decoder. This decoding approach operates by processing, in parallel, selected rows for multiple individual LDPC matrix rows from various sub-matrix rows (e.g., first group of rows from a first sub-matrix row, second group of rows from a second sub-matrix row, etc.). A memory structure of daisy chains is employed for memory management of APP (a posteriori probability) values and also for check edge messages/intrinsic information (λ) values. A first group of daisy chains may be employed for memory management of the APP values, and a second group of daisy chains may be employed for memory management of the check edge messages. These daisy chains operate to effectuate the proper alignment of APP (or gamma(γ)) values and check edge message/intrinsic information (λ) values for their respective updating in successive decoding iterations.
摘要翻译：加密LDPC（低密度奇偶校验）解码器。该解码方法通过并行处理来自各种子矩阵行的多个单独LDPC矩阵行的选择行（例如，来自第一子矩阵行的第一组行，来自第二子矩阵行的第二组行等）。菊花链的存储器结构被用于APP（后验概率）值的存储器管理，也用于校验边消息/固有信息（λ）值。第一组菊花链可用于APP值的存储器管理，并且可以采用第二组菊花链来进行校验边消息的存储器管理。这些菊花链用于在连续的解码迭代中实现APP（或γ（γ））值的正确对齐并检查边缘消息/固有信息（λ）值以用于它们各自的更新。

5. 发明授权

US08171375B2 Distributed processing LDPC (low density parity check) decoder 有权
标题翻译：分布式处理LDPC（低密度奇偶校验）解码器
公开(公告)号：US08171375B2
公开(公告)日：2012-05-01
申请号：US13096114
申请日：2011-04-28
申请人： Alvin Lai Lin , Andrew J. Blanksby
发明人： Alvin Lai Lin , Andrew J. Blanksby
IPC分类号： H03M13/00
CPC分类号： H03M13/6516 , H03M13/1111 , H03M13/1137 , H03M13/6505
摘要： Distributed processing LDPC (Low Density Parity Check) decoder. A means is presented herein that includes an LDPC decoding architecture leveraging a distributed processing technique (e.g., daisy chain) to increase data throughput and reduce memory storage requirements. Routing congestion and critical path latency are also improved thereby. Each daisy chain includes a number of registers, and a number of localized MUXs (e.g., MUXs having merely 2 inputs each). The means presented herein also does not contain any barrel shifters, high fan-in multiplexers, or interconnection networks; therefore, the critical path is relatively short and it can also be pipelined to further increase data throughput. If desired, a communication device can include multiple configurations of such daisy chains to accommodate the decoding of various LDPC coded signals (e.g., such as for an application and/or communication device that must decoded LDPC codes using different low density parity check matrices).
摘要翻译：分布式处理LDPC（低密度奇偶校验）解码器。本文提供了一种包括利用分布式处理技术（例如，菊花链）来增加数据吞吐量并减少存储器存储需求的LDPC解码架构的手段。路由拥塞和关键路径延迟也因此得到改善。每个菊花链包括多个寄存器和多个本地化MUX（例如，每个仅具有2个输入的MUX）。本文中提供的方法也不包含任何桶形移位器，高风扇多路复用器或互连网络; 因此，关键路径相对较短，并且还可以流水线化以进一步增加数据吞吐量。如果需要，通信设备可以包括这种菊花链的多种配置，以适应各种LDPC编码信号（例如，对于应用和/或通信设备的解码，该应用和/或通信设备必须使用不同的低密度奇偶校验矩阵解码LDPC码）。

6. 发明申请

US20090013239A1 LDPC (Low Density Parity Check) decoder employing distributed check and/or variable node architecture 审中-公开
标题翻译：采用分布式检查和/或可变节点架构的LDPC（低密度奇偶校验）解码器
公开(公告)号：US20090013239A1
公开(公告)日：2009-01-08
申请号：US11830639
申请日：2007-07-30
申请人： Andrew J. Blanksby
发明人： Andrew J. Blanksby
IPC分类号： G06F11/00
CPC分类号： H03M13/1111
摘要： LDPC (Low Density Parity Check) decoder employing distributed check into variable node architecture. A means of decoding processing is presented in which at least one portion of the check node processing functionality is actually integrated into the variable/bit node processing functionality (e.g., distributed check node embodiment). In alternative embodiments, at least one portion of the variable/bit node processing functionality is actually integrated into the check node processing functionality (e.g., distributed variable/bit node embodiment). In even other embodiments, some check node processing functionality is moved and integrated into the variable/bit node processing functionality, and some variable/bit node processing functionality is also moved and integrated into the check node processing functionality (e.g., combined distributed embodiment). It is also noted that, when appropriately selected, the modification of the check engine and bit engine can also allow for reduction in routing layout between such a check engine and bit engine within a communication device.
摘要翻译： LDPC（Low Density Parity Check，低密度奇偶校验）解码器采用分布式校验转换为可变节点架构。呈现解码处理的手段，其中校验节点处理功能的至少一部分实际上被集成到可变/位节点处理功能（例如，分布式校验节点实施例）中。在替代实施例中，可变/位节点处理功能的至少一部分实际上被集成到校验节点处理功能（例如，分布式变量/位节点实施例）中。在甚至其他实施例中，一些校验节点处理功能被移动并被集成到可变/位节点处理功能中，并且一些可变/位节点处理功能也被移动并被集成到校验节点处理功能（例如，组合分布式实施例）中。还应注意的是，当适当选择时，检查引擎和位引擎的修改还可以允许减少通信设备内的这种检查引擎和位引擎之间的布线布局。

7. 发明申请

US20130139026A1 ACCUMULATING LDPC (LOW DENSITY PARITY CHECK) DECODER 失效
标题翻译：累积LDPC（低密度奇偶校验）解码器
公开(公告)号：US20130139026A1
公开(公告)日：2013-05-30
申请号：US13726159
申请日：2012-12-23
申请人： Andrew J. Blanksby , Alvin Lai Lin
发明人： Andrew J. Blanksby , Alvin Lai Lin
IPC分类号： H03M13/13
CPC分类号： H03M13/13 , H03M13/1137 , H03M13/1145 , H03M13/116 , H04L1/005 , H04L1/0057
摘要： The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.
摘要翻译：本文描述的累积解码架构可应用于由奇偶校验矩阵H操作的LDPC码，H由CSI（循环移位身份）子矩阵（或矩阵子块）或置换的身份子矩阵（或矩阵子块）。在这种结构中，整个LDPC矩阵被分解为方形子矩阵，使得每个子矩阵由CSI子矩阵或置换的身份子矩阵或空矩阵组成。迭代解码过程通过更新APP（后验概率）或伽马（gamma）值和检查边缘消息（lambda）值来操作，并且这通过更新多个子矩阵行（或全部子帧）中的一个或多个单独的行来操作 - 矩阵或子块行）并行处理。并行度由设计者指定，通常是子矩阵（或子块）大小的整数除数。

8. 发明授权

US08392787B2 Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding 有权
公开(公告)号：US08392787B2
公开(公告)日：2013-03-05
申请号：US12561374
申请日：2009-09-17
申请人： Ba-Zhong Shen , Andrew J. Blanksby , Jason A. Trachewsky
发明人： Ba-Zhong Shen , Andrew J. Blanksby , Jason A. Trachewsky
IPC分类号： H03M13/11 , H03M13/33
CPC分类号： H03M13/616 , H03M13/033 , H03M13/1137 , H03M13/114 , H03M13/1148 , H03M13/116 , H03M13/13 , H03M13/635 , H03M13/6516 , H04L1/0057
摘要： Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding. Multiple LDPC matrices may be generated from a base code, such that multiple/distinct LDPC coded signals may be encoded and/or decoded within a singular communication device. Generally speaking, a first LDPC matrix is modified in accordance with one or more operations thereby generating a second LDPC matrix, and the second LDPC matrix is employed in accordance with encoding an information bit thereby generating an LDPC coded signal (alternatively performed using an LDPC generator matrix corresponding to the LDPC matrix) and/or decoding processing of an LDPC coded signal thereby generating an estimate of an information bit encoded therein. The operations performed on the first LDPC matrix may be any one of, or combination of, selectively merging, deleting, partially re-using one or more sub-matrix rows, and/or partitioning sub-matrix rows.

9. 发明授权

US08392786B2 LDPC coding systems for 60 GHz millimeter wave based physical layer extension 有权
公开(公告)号：US08392786B2
公开(公告)日：2013-03-05
申请号：US12435821
申请日：2009-05-05
申请人： Jason A. Trachewsky , Ba-Zhong Shen , Andrew J. Blanksby , Joonsuk Kim
发明人： Jason A. Trachewsky , Ba-Zhong Shen , Andrew J. Blanksby , Joonsuk Kim
IPC分类号： H03M13/00 , H03M13/03
CPC分类号： H04L1/0041 , H03M13/116 , H03M13/1185 , H03M13/6544 , H03M13/655 , H04L1/005 , H04L1/0057 , H04L1/0065 , H04L1/0071
摘要： LDPC coding systems for 60 GHz millimeter wave based physical layer extension. LDPC (Low Density Parity Check) encoding in cooperation with sub-carrier interleaving, in the context of orthogonal frequency division multiplexing (OFDM), and appropriate symbol mapping is performed in accordance with transmit processing as may be performed within a communication device. In a receiving communication device, receive processing may be performed on a received signal based on the type of LDPC, sub-carrier interleaving, and symbol mapping thereof. The LDPC code employed in accordance with such LDPC encoding may have a partial-tree like structure. In addition, appropriate manipulation of the bits assigned to respective sub-carriers may be performed to ensure that the bits emplaced in the MSB (Most Significant Bit) location of various symbols has some desired diversity (e.g., from different codewords, from appropriately different locations within a given codeword, etc.).

10. 发明授权

US08341488B2 Accumulating LDPC (low density parity check) decoder 有权
标题翻译：累积LDPC（低密度奇偶校验）解码器
公开(公告)号：US08341488B2
公开(公告)日：2012-12-25
申请号：US12512490
申请日：2009-07-30
申请人： Andrew J. Blanksby , Alvin Lai Lin
发明人： Andrew J. Blanksby , Alvin Lai Lin
IPC分类号： H03M13/00
CPC分类号： H03M13/13 , H03M13/1137 , H03M13/1145 , H03M13/116 , H04L1/005 , H04L1/0057
摘要： Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.
摘要翻译：累积LDPC（低密度奇偶校验）解码器。本文描述的累积解码架构可应用于由奇偶校验矩阵H操作的LDPC码，H由CSI（循环移位身份）子矩阵（或矩阵子块）或置换的身份子矩阵（或矩阵子块）。在这种结构中，整个LDPC矩阵被分解为方形子矩阵，使得每个子矩阵由CSI子矩阵或置换的身份子矩阵或空矩阵组成。迭代解码过程通过更新APP（后验概率）或γ（γ）值并检查边缘消息（λ）值来操作，并且通过更新多个子矩阵行（或全部子帧）中的一个或多个单独行 - 矩阵或子块行）并行处理。并行度由设计者指定，通常是子矩阵（或子块）大小的整数除数。

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