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1. 发明授权

US08773925B2 Multilevel DRAM 有权
标题翻译：多级DRAM
公开(公告)号：US08773925B2
公开(公告)日：2014-07-08
申请号：US13578498
申请日：2010-12-01
申请人： Yoshihito Koya , Brent Haukness
发明人： Yoshihito Koya , Brent Haukness
IPC分类号： G11C7/10
CPC分类号： G11C7/16 , G11C11/401 , G11C11/4091 , G11C11/4097 , G11C11/565 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2207/005 , G11C2207/2254
摘要： A multi-level dynamic random-access memory (MLDRAM) represents an original bit combination of more than one bit using a cell voltage stored in a single memory cell. The cell voltage is in one of a number of discrete analog voltage ranges each corresponding to a respective one of the possible values of the bit combination. In reading a selected memory cell, stored charge is conveyed via a local bitline to a preamplifier. The preamplifier amplifies the signal on the local bitline and drives a global bitline with an analog signal representative of the stored voltage. A digitizer converts the analog signal on the global bitline into a read bit combination. The read bit combination is then moved to a data cache over the global bitline. The data cache writes an analog voltage back to the memory cell to write a new value or restore data destroyed in reading the cell.
摘要翻译：多级动态随机存取存储器（MLDRAM）使用存储在单个存储器单元中的单元电压来表示多于一位的原始位组合。电池电压是多个离散的模拟电压范围之一，每个对应于位组合的可能值的相应一个。在读取所选存储单元时，存储的电荷通过本地位线被传送到前置放大器。前置放大器放大本地位线上的信号，并用表示存储电压的模拟信号驱动全局位线。数字转换器将全局位线上的模拟信号转换为读位组合。读取位组合然后通过全局位线移动到数据高速缓存。数据高速缓存将模拟电压写入存储单元以写入新值或恢复在读取单元格时销毁的数据。

2. 发明申请

US20080184005A1 METHODS AND APPARATUS FOR USING A CONFIGURATION ARRAY SIMILAR TO AN ASSOCIATED DATA ARRAY 有权
标题翻译：使用类似于相关数据阵列的配置阵列的方法和装置
公开(公告)号：US20080184005A1
公开(公告)日：2008-07-31
申请号：US11669923
申请日：2007-01-31
申请人： Tyler Thorp , Brent Haukness
发明人： Tyler Thorp , Brent Haukness
IPC分类号： G06F12/04
CPC分类号： G11C16/20 , G11C5/02
摘要： Methods, apparatus, and systems for memories that include a data array and a configuration array adapted to store configuration information for configuring the data array, are disclosed. The data array and the configuration array include a plurality of wordlines and a plurality of bitlines. The plurality of wordlines in the data array extend in the same direction as the plurality of wordlines in the configuration array. Likewise, the plurality of bitlines in the data array extend in the same direction as the plurality of bitlines in the configuration array. The configuration array may include a wordline driver layout, a bitline driver layout, relative positions of zia contact regions, a diode sensing orientation, a sense amplifier layout, a voltage regulator layout, and a layout of conductors proximate to the array that are each substantially similar to corresponding elements of the data array. Numerous other aspects are disclosed.
摘要翻译：公开了包括适于存储用于配置数据阵列的配置信息的数据阵列和配置阵列的用于存储器的方法，装置和系统。数据阵列和配置阵列包括多个字线和多个位线。数据阵列中的多个字线在与配置阵列中的多个字线相同的方向上延伸。类似地，数据阵列中的多个位线沿与配置阵列中的多个位线方向相同的方向延伸。配置阵列可以包括字线驱动器布局，位线驱动器布局，zia接触区域的相对位置，二极管感测定向，读出放大器布局，电压调节器布局以及靠近阵列的导体的布局，类似于数据数组的相应元素。公开了许多其他方面。

3. 发明申请

US20080184004A1 METHODS AND APPARATUS FOR USING A CONFIGURATION ARRAY SIMILAR TO AN ASSOCIATED DATA ARRAY 有权
公开(公告)号：US20080184004A1
公开(公告)日：2008-07-31
申请号：US11669919
申请日：2007-01-31
申请人： Tyler Thorp , Brent Haukness
发明人： Tyler Thorp , Brent Haukness
IPC分类号： G06F12/00
CPC分类号： G11C7/1045 , G11C13/025 , H01L27/0203 , H01L27/105
摘要： Methods, apparatus, and systems for memories that include a data array and a configuration array adapted to store configuration information for configuring the data array, are disclosed. The data array and the configuration array include a plurality of wordlines and a plurality of bitlines. The plurality of wordlines in the data array extend in the same direction as the plurality of wordlines in the configuration array. Likewise, the plurality of bitlines in the data array extend in the same direction as the plurality of bitlines in the configuration array. The configuration array may include a wordline driver layout, a bitline driver layout, relative positions of zia contact regions, a diode sensing orientation, a sense amplifier layout, a voltage regulator layout, and a layout of conductors proximate to the array that are each substantially similar to corresponding elements of the data array. Numerous other aspects are disclosed.

4. 发明申请

US20080013411A1 Electronic Library for Managing Data on Removable Storage Devices 有权
标题翻译：用于管理可移动存储设备数据的电子图书馆
公开(公告)号：US20080013411A1
公开(公告)日：2008-01-17
申请号：US11677388
申请日：2007-02-21
申请人： Tyler Thorp , Brent Haukness , Henry Hutton
发明人： Tyler Thorp , Brent Haukness , Henry Hutton
IPC分类号： G11B21/08 , G06F13/00
CPC分类号： G06F3/0664 , G06F3/0607 , G06F3/0679 , G06F3/0688
摘要： An electronic library for managing data from removable data storage devices is described. The electronic library may have a stand-alone housing with a plurality of receptacles, at least two of the receptacles sized to connect with at least a first type of removable data storage device. An interface positioned on the housing permits concurrent access to removable data storage devices connected with the plurality of receptacles. A data access module in the housing may be configured to emulate a single removable data storage device containing data folders with corresponding to each removable data storage device. A refresh module in the housing may be configured to refresh each memory address of a removable data storage device in communication with one of the plurality of receptacles so that data integrity may be preserved.
摘要翻译：描述了用于从可移动数据存储设备管理数据的电子库。电子图书馆可以具有带有多个插座的独立外壳，至少两个插座的尺寸设计成与至少第一类型的可拆卸数据存储装置连接。位于壳体上的界面允许同时访问与多个插座连接的可移动数据存储设备。壳体中的数据访问模块可以被配置为模拟包含与每个可移除数据存储设备相对应的数据文件夹的单个可移除数据存储设备。外壳中的刷新模块可以被配置为刷新与多个插座之一通信的可移动数据存储设备的每个存储器地址，从而可以保持数据完整性。

5. 发明授权

US07149845B2 Current mode logic scheme and circuit for matchline sense amplifier design using constant current bias cascode current mirrors 有权
标题翻译：电流模式逻辑方案和电路，用于使用恒流偏置共源共栅电流镜的匹配线读出放大器设计
公开(公告)号：US07149845B2
公开(公告)日：2006-12-12
申请号：US10733474
申请日：2003-12-12
申请人： Kit Fai Chan , Brent Haukness
发明人： Kit Fai Chan , Brent Haukness
IPC分类号： G06F12/00 , G11C15/00
CPC分类号： G11C15/043 , G11C15/04
摘要： A CAM device features matchlines which are coupled in series between a top current source, a bottom current source, and ground. The top current source is configured to supply a first current to the matchline and the bottom current source, while the bottom current source is configured to supply a second current to ground. The magnitude of the first current is limited by the operation of the CAM cells coupled to the matchline, and is duplicated by a current mirror architecture. The mirrored of the first current, known as the sense current, is coupled to a measurement circuit to measure the state of the matchline. This architecture features lower power consumption and faster matchline evaluations.
摘要翻译： CAM设备具有在顶部电流源，底部电流源和地之间串联耦合的匹配线。顶部电流源被配置为向匹配线和底部电流源提供第一电流，而底部电流源被配置为向接地提供第二电流。第一电流的大小受耦合到匹配线的CAM单元的操作的限制，并且由当前镜架结构复制。被称为感测电流的第一电流的镜像耦合到测量电路以测量匹配线的状态。该架构具有较低的功耗和更快的匹配线评估。

6. 发明申请

US20130215669A1 RESISTANCE CHANGE MEMORY CELL CIRCUITS AND METHODS 有权
标题翻译：电阻变化记忆体电路和方法
公开(公告)号：US20130215669A1
公开(公告)日：2013-08-22
申请号：US13882130
申请日：2011-10-26
申请人： Brent Haukness
发明人： Brent Haukness
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C8/08 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C13/0097 , G11C2013/0045 , G11C2013/0071 , G11C2013/0078 , G11C2213/79
摘要： The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.
摘要翻译： 1晶体管1电阻（1T1R）型RRAM单元的存取晶体管的栅极使用电流镜相对于存取晶体管的源极偏置。在跨过1T1R单元（例如经由位线）施加的电压的影响下，RRAM存储元件从较高的电阻切换到较低的电阻。当RRAM存储元件从较高的电阻切换到较低电阻时，通过RRAM单元的电流基本上由RRAM器件的较高电阻（而存取晶体管在线性区域中工作）基本确定为基本确定通过存取晶体管的饱和区工作点。

7. 发明授权

US07870472B2 Methods and apparatus for employing redundant arrays to configure non-volatile memory 有权
标题翻译：采用冗余阵列配置非易失性存储器的方法和装置
公开(公告)号：US07870472B2
公开(公告)日：2011-01-11
申请号：US11669918
申请日：2007-01-31
申请人： Tyler Thorp , Brent Haukness
发明人： Tyler Thorp , Brent Haukness
IPC分类号： G06F11/18 , G06F11/24
CPC分类号： G06F11/183 , G11C16/20
摘要： Systems, methods and apparatus are disclosed for employing redundant arrays to configure non-volatile memory. The present invention may include a substrate including a plurality of memory arrays, wherein the memory arrays include a data array and at least three redundant configuration arrays. The configuration arrays may each be adapted to be programmed with identical configuration information associated with operation of the data array. Majority voting logic with an output coupled to configuration inputs of the data array and inputs coupled to each of the redundant configuration arrays may be employed. The majority voting logic may be adapted to determine a configuration for the data array based upon an outcome of a majority vote function applied to the configuration information stored in the configuration arrays. Numerous other aspects are disclosed.
摘要翻译：公开了采用冗余阵列来配置非易失性存储器的系统，方法和装置。本发明可以包括包括多个存储器阵列的衬底，其中存储器阵列包括数据阵列和至少三个冗余配置阵列。配置阵列可以各自适于用与数据阵列的操作相关联的相同配置信息进行编程。可以采用多数投票逻辑，其输出耦合到数据阵列的配置输入和耦合到每个冗余配置阵列的输入。多数投票逻辑可以适于基于应用于存储在配置数组中的配置信息的多数投票函数的结果来确定数据阵列的配置。公开了许多其他方面。

8. 发明授权

US07870471B2 Methods and apparatus for employing redundant arrays to configure non-volatile memory 有权
公开(公告)号：US07870471B2
公开(公告)日：2011-01-11
申请号：US11669917
申请日：2007-01-31
申请人： Tyler Thorp , Brent Haukness
发明人： Tyler Thorp , Brent Haukness
IPC分类号： G06F11/18
CPC分类号： G06F11/183 , G11C16/20 , G11C29/74 , G11C29/802
摘要： Systems, methods and apparatus are disclosed for employing redundant arrays to configure non-volatile memory. The present invention may include a substrate including a plurality of memory arrays, wherein the memory arrays include a data array and at least three redundant configuration arrays. The configuration arrays may each be adapted to be programmed with identical configuration information associated with operation of the data array. Majority voting logic with an output coupled to configuration inputs of the data array and inputs coupled to each of the redundant configuration arrays may be employed. The majority voting logic may be adapted to determine a configuration for the data array based upon an outcome of a majority vote function applied to the configuration information stored in the configuration arrays. Numerous other aspects are disclosed.

9. 发明申请

US20070216448A1 APPARATUS FOR ADAPTIVE TRIP POINT DETECTION 有权
标题翻译：自适应三点检测装置
公开(公告)号：US20070216448A1
公开(公告)日：2007-09-20
申请号：US11752807
申请日：2007-05-23
申请人： Tyler Thorp , Mark Johnson , Brent Haukness
发明人： Tyler Thorp , Mark Johnson , Brent Haukness
IPC分类号： H03K17/00
CPC分类号： H03K5/153 , H03K17/145 , H03K17/223
摘要： Apparatus are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature.
摘要翻译：描述了用于提供自适应跳变点检测器电路的装置，其接收输入信号节点处的输入信号并在输出信号节点处产生输出信号，当输入信号超过一个输入信号时，该输出信号从第一值变为第二值跳点参考值。特别地，调整跳变点参考值以补偿过程或温度的变化。

10. 发明授权

US07236023B2 Apparatus and methods for adaptive trip point detection 有权
标题翻译：自适应跳变点检测的装置和方法
公开(公告)号：US07236023B2
公开(公告)日：2007-06-26
申请号：US11106288
申请日：2005-04-14
申请人： Tyler J. Thorp , Mark G. Johnson , Brent Haukness
发明人： Tyler J. Thorp , Mark G. Johnson , Brent Haukness
IPC分类号： H03L7/00
CPC分类号： H03K5/153 , H03K17/145 , H03K17/223
摘要： Apparatus and methods are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature, without requiring an externally-supplied reference signal.
摘要翻译：描述了用于提供自适应跳变点检测器电路的装置和方法，所述自适应跳变点检测器电路在输入信号节点处接收输入信号，并在输出信号节点处产生输出信号，输出信号在第一值变化到第二值时，超过跳点参考值。特别地，调整跳变点参考值以补偿过程或温度的变化，而不需要外部提供的参考信号。

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