专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07236023B2 Apparatus and methods for adaptive trip point detection 有权
标题翻译：自适应跳变点检测的装置和方法
公开(公告)号：US07236023B2
公开(公告)日：2007-06-26
申请号：US11106288
申请日：2005-04-14
申请人： Tyler J. Thorp , Mark G. Johnson , Brent Haukness
发明人： Tyler J. Thorp , Mark G. Johnson , Brent Haukness
IPC分类号： H03L7/00
CPC分类号： H03K5/153 , H03K17/145 , H03K17/223
摘要： Apparatus and methods are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature, without requiring an externally-supplied reference signal.
摘要翻译：描述了用于提供自适应跳变点检测器电路的装置和方法，所述自适应跳变点检测器电路在输入信号节点处接收输入信号，并在输出信号节点处产生输出信号，输出信号在第一值变化到第二值时，超过跳点参考值。特别地，调整跳变点参考值以补偿过程或温度的变化，而不需要外部提供的参考信号。

2. 发明授权

US07863951B2 Methods for adaptive trip point detection 有权
标题翻译：自适应跳变点检测方法
公开(公告)号：US07863951B2
公开(公告)日：2011-01-04
申请号：US11752819
申请日：2007-05-23
申请人： Tyler J. Thorp , Mark G. Johnson , Brent Haukness
发明人： Tyler J. Thorp , Mark G. Johnson , Brent Haukness
IPC分类号： H03L7/00
CPC分类号： H03K5/153 , H03K17/145 , H03K17/223
摘要： Methods are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature.
摘要翻译：描述了用于提供自适应跳变点检测器电路的方法，该电路在输入信号节点处接收输入信号并在输出信号节点处产生输出信号，当输入信号超过一个输入信号时，该输出信号从第一值变为第二值跳点参考值。特别地，调整跳变点参考值以补偿过程或温度的变化。

3. 发明授权

US07863950B2 Apparatus for adaptive trip point detection 有权
标题翻译：自适应跳变点检测装置
公开(公告)号：US07863950B2
公开(公告)日：2011-01-04
申请号：US11752807
申请日：2007-05-23
申请人： Tyler J. Thorp , Mark G. Johnson , Brent Haukness
发明人： Tyler J. Thorp , Mark G. Johnson , Brent Haukness
IPC分类号： H03L7/00
CPC分类号： H03K5/153 , H03K17/145 , H03K17/223
摘要： Apparatus are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature.
摘要翻译：描述了用于提供自适应跳变点检测器电路的装置，其接收输入信号节点处的输入信号并在输出信号节点处产生输出信号，当输入信号超过一个输入信号时，该输出信号从第一值变为第二值跳点参考值。特别地，调整跳变点参考值以补偿过程或温度的变化。

4. 发明申请

US20110156044A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 审中-公开
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20110156044A1
公开(公告)日：2011-06-30
申请号：US13027113
申请日：2011-02-14
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L29/786 , H01L29/78
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

5. 发明授权

US07308065B2 Delay locked loop circuitry for clock delay adjustment 失效
标题翻译：延迟锁定环电路，用于时钟延迟调整
公开(公告)号：US07308065B2
公开(公告)日：2007-12-11
申请号：US11406557
申请日：2006-04-18
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
IPC分类号： H03D3/24 , H03L7/06
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.
摘要翻译：适于耦合到数据总线并被配置为根据接收时钟接收数据的接收机包括第一和第二延迟锁定环路。第一延迟锁定环路被配置为从第一参考时钟产生多个相位矢量，并且第二延迟锁定环路耦合到第一延迟锁定环路并且被配置为从至少一个相位矢量生成接收时钟从所述多个相位矢量中选择并具有第二参考时钟。

6. 发明授权

US07283403B2 Memory device and method for simultaneously programming and/or reading memory cells on different levels 失效
标题翻译：用于同时编程和/或读取不同级别的存储单元的存储器件和方法
公开(公告)号：US07283403B2
公开(公告)日：2007-10-16
申请号：US10987091
申请日：2004-11-12
申请人： Mark G. Johnson
发明人： Mark G. Johnson
IPC分类号： G11C7/00
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

7. 发明授权

US07177183B2 Multiple twin cell non-volatile memory array and logic block structure and method therefor 有权
标题翻译：多个单元非易失性存储器阵列及其逻辑块结构及其方法
公开(公告)号：US07177183B2
公开(公告)日：2007-02-13
申请号：US10675212
申请日：2003-09-30
申请人： Roy E. Scheuerlein , Luca Fasoli , Mark G. Johnson
发明人： Roy E. Scheuerlein , Luca Fasoli , Mark G. Johnson
IPC分类号： G11C16/04
CPC分类号： G11C15/046 , G11C8/10 , G11C8/14 , G11C16/10 , G11C16/16
摘要： Extremely dense memory cell structures provide for new array structures useful for implementing memory and logic functions. An exemplary non-volatile memory array includes a first plurality of X-lines configured to be logically identical in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line. Each of the first plurality of X-lines may also be associated with a second Y-line group numbering at least one Y-line. In some embodiments, the first and second Y-Line groups are simultaneously selectable in a read mode and, when so selected, are respectively coupled to true and complement inputs of a sense amplifier circuit. Such Y-line groups may number only one Y-line, or may number more than one Y-line. Many types of memory cells may be used, such as various passive element cells and EEPROM cells, in both 2D or 3D memory arrays. Such arrays may be configured as a memory to store data, or configured to perform threshold logic, or configured as a content addressable memory array.
摘要翻译：非常密集的存储单元结构提供了用于实现内存和逻辑功能的新数组结构。示例性非易失性存储器阵列包括被配置为在读取操作模式下在逻辑上相同的第一多个X线，并且每个X线与与至少一个Y线编号的第一Y线组相关联。第一多个X线中的每一个也可以与编号至少一个Y线的第二Y线组相关联。在一些实施例中，第一和第二Y线组可以以读取模式同时选择，并且当这样选择时，它们分别耦合到读出放大器电路的真实和补码输入。这样的Y线组可以仅编号一条Y线，或者可以编号多于一条Y线。可以在2D或3D存储器阵列中使用许多类型的存储单元，例如各种无源元件单元和EEPROM单元。这样的阵列可以被配置为存储数据，或被配置为执行阈值逻辑或被配置为内容可寻址存储器阵列的存储器。

8. 发明授权

US07129538B2 Dense arrays and charge storage devices 有权
公开(公告)号：US07129538B2
公开(公告)日：2006-10-31
申请号：US10842008
申请日：2004-05-10
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul M. Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul M. Farmwald , Brad Herner
IPC分类号： H01L29/788
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

9. 发明授权

US06901549B2 Method for altering a word stored in a write-once memory device 失效
标题翻译：用于改变存储在一次写入存储器件中的字的方法
公开(公告)号：US06901549B2
公开(公告)日：2005-05-31
申请号：US10023200
申请日：2001-12-14
申请人： Roger W. March , Christopher S. Moore , Mark G. Johnson
发明人： Roger W. March , Christopher S. Moore , Mark G. Johnson
IPC分类号： G11C7/10 , G11C7/24 , G11C17/14 , H03M13/00
CPC分类号： G11C17/146 , G11C7/1006 , G11C7/24 , G11C17/14
摘要： The preferred embodiments described herein provide a method for altering a word stored in a write-once memory device. In one preferred embodiment, a write-once memory device is provided storing a word comprising a plurality of data bits and a plurality of syndrome bits. The word is altered by identifying X bit(s) in the word that are in an un-programmed state and switching the X bit(s) from the un-programmed state to a programmed state, where X is sufficient to introduce an uncorrectable error in the word. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
摘要翻译：本文所述的优选实施例提供了一种用于改变存储在一次写入存储器件中的字的方法。在一个优选实施例中，提供了一次写入存储器件，其存储包括多个数据位和多个校正子位的字。通过识别字处于非编程状态的X位，并将X位从未编程状态切换到编程状态来改变该字，其中X足以引入不可校正的错误在这个词中。提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。

10. 发明授权

US06525949B1 Charge pump circuit 有权
公开(公告)号：US06525949B1
公开(公告)日：2003-02-25
申请号：US09748815
申请日：2000-12-22
申请人： Mark G. Johnson , Joseph G. Nolan, III , Matthew P. Crowley
发明人： Mark G. Johnson , Joseph G. Nolan, III , Matthew P. Crowley
IPC分类号： H02M318
CPC分类号： H02M3/073
摘要： A charge pump circuit includes, in a preferred embodiment, a plurality of serially-connected pump stages, each of which is driven by one or more associated clock signals for the stage. The amplitude of the clock signals associated with a respective one of the pump stages differ in amplitude from that of the clock signals associated with at least one other pump stage. As a result, the additional voltage achieved by each successive pump stage may be progressively larger for each successive pump stage. An exemplary charge pump circuit provides clock signals which increase in amplitude with each successive pump stage, and provides with each successive pump stage an output voltage having a magnitude that is a multiplicative factor of the magnitude of the input voltage for the stage. Consequently, the output voltage achieved by the exemplary charge pump circuit is an exponential function of the number of pump stages within the charge pump circuit.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式