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1. 发明授权

US08868873B2 Reconfigurable memory system data strobes 有权
标题翻译：可重构内存系统数据选通
公开(公告)号：US08868873B2
公开(公告)日：2014-10-21
申请号：US12678739
申请日：2008-08-25
申请人： Ian Shaeffer , Frederick Ware , Craig E. Hampel
发明人： Ian Shaeffer , Frederick Ware , Craig E. Hampel
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F13/16
CPC分类号： G06F3/0634 , G06F3/0665 , G06F3/0689 , G06F13/1694 , G06F2212/262 , G11C7/22
摘要： In a reconfigurable data strobe-based memory system, data strobes may be re-tasked in different modes of operation. For example, in one mode of operation a differential data strobe may be used as a timing reference for a given set of data signals. In a second mode of operation, one of the components of the differential data strobe may be used as a timing reference for a first portion of the set of data signals and the other component used as a timing reference for a second portion of the set of data signals. Different data mask-related schemes also may be invoked for different modes of operation. For example, in a first mode of operation a memory controller may generate a data mask signal to prevent a portion of a set of data from being written to a memory array. Then, in a second mode of operation the memory controller may invoke a coded value replacement scheme or a data strobe transition inhibition scheme to prevent a portion of a set of data from being written to a memory array.
摘要翻译：在可重新配置的基于数据选通的存储器系统中，数据选通可以在不同的操作模式下重新安排。例如，在一种操作模式中，差分数据选通可以用作给定的一组数据信号的定时参考。在第二操作模式中，可以将差分数据选通的一个组件用作数据信号组的第一部分的定时参考，另一组件用作该组数据信号的第二部分的定时参考数据信号。也可以针对不同的操作模式调用不同的数据掩码相关方案。例如，在第一操作模式中，存储器控制器可以生成数据掩码信号以防止一组数据被写入存储器阵列。然后，在第二操作模式中，存储器控制器可以调用编码值替换方案或数据选通转换禁止方案，以防止一组数据被写入存储器阵列。

2. 发明授权

US08560797B2 Method and apparatus for indicating mask information 有权
标题翻译：用于指示掩模信息的方法和装置
公开(公告)号：US08560797B2
公开(公告)日：2013-10-15
申请号：US13421701
申请日：2012-03-15
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasborro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasborro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.
摘要翻译：一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括一个接口，用于在第一组多条引线上向DRAM发送一个第一代码，以指示第一个数据要写入DRAM，列地址以指示要写入第一数据的DRAM中的存储器核的列位置。该接口还用于发送第二代码以指示是否将第一数据的掩码信息发送到DRAM。如果第二代码指示将发送掩码信息，则在发送第二代码之后发送列地址的一部分和掩码信息的一部分。接口进一步通过与第一多个电线分开的第二多个电线将DRAM发送到第一数据。

3. 发明授权

US08537601B2 Memory controller with selective data transmission delay 有权
标题翻译：具有选择性数据传输延迟的存储控制器
公开(公告)号：US08537601B2
公开(公告)日：2013-09-17
申请号：US13543779
申请日：2012-07-06
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C11/24
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A DRAM controller component generates a timing signal and transmits, to a DRAM, write data that requires a first time interval to propagate from the DRAM controller component to the DRAM and to be sampled by the DRAM on one or more edges of the timing signal, a clock signal that requires a second time interval to propagate from the DRAM controller component to the DRAM, and a write command, associated with the write data, to be sampled by the DRAM on one or more edges of the clock signal. The DRAM controller component includes series-coupled delay elements to generate respective incrementally delayed signals, and a multiplexer to select one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval.
摘要翻译： DRAM控制器部件产生定时信号，并且向DRAM发送需要第一时间间隔从DRAM控制器部件传播到DRAM并由DRAM在定时信号的一个或多个边缘进行采样的写入数据，需要第二时间间隔从DRAM控制器部件传播到DRAM的时钟信号以及与写入数据相关联的写入命令，以由DRAM在时钟信号的一个或多个边缘上采样。 DRAM控制器组件包括串联耦合的延迟元件以产生相应的递增延迟的信号，以及多路复用器，用于选择延迟信号中的一个来对写入数据进行传输，以便写入数据的传输基于第一时间间隔和第二时间间隔。

4. 发明授权

US08295107B2 Asynchronous pipelined memory access 失效
标题翻译：异步流水线内存访问
公开(公告)号：US08295107B2
公开(公告)日：2012-10-23
申请号：US13281436
申请日：2011-10-26
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： A plurality of control signals are asserted within an asynchronous integrated circuit memory device in response to each transition of a memory access initiation signal to effect pipelined memory access operations.
摘要翻译：多个控制信号在异步集成电路存储器件内响应于存储器访问启动信号的每个转换而被执行以实现流水线存储器访问操作。

5. 发明授权

US08248884B2 Method of controlling a memory device having multiple power modes 有权
标题翻译：控制具有多个功率模式的存储器件的方法
公开(公告)号：US08248884B2
公开(公告)日：2012-08-21
申请号：US12975322
申请日：2010-12-21
申请人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
发明人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device includes a clock receiver, a command interface, and a data interface separate from the command interface. A memory controller provides the command interface with a command that specifies a write operation. After a programmable latency period transpires from providing the command, data associated with the write operation is provided to the data interface by the memory controller. The memory controller provides power mode information that controls transitions between a plurality of power modes, where for each power mode of the plurality of power modes, less power is consumed than the amount of power consumed during the write operation. The power modes include a mode in which the clock receiver is on and the data interface is off; and a mode in which the clock receiver is off and the data interface is off.
摘要翻译：存储器件包括时钟接收器，命令接口和与命令接口分开的数据接口。存储器控制器为命令接口提供指定写入操作的命令。在从提供命令开始可编程的等待时间之后，由写入操作相关联的数据由存储器控制器提供给数据接口。存储器控制器提供功率模式信息，其控制多个功率模式之间的转换，其中对于多个功率模式的每个功率模式，消耗的功率比在写入操作期间消耗的功率量少。功率模式包括时钟接收器接通和数据接口关闭的模式; 以及时钟接收器关闭且数据接口关闭的模式。

6. 发明申请

US20120173811A1 Method and Apparatus for Delaying Write Operations 审中-公开
标题翻译：延迟写入操作的方法和装置
公开(公告)号：US20120173811A1
公开(公告)日：2012-07-05
申请号：US13421753
申请日：2012-03-15
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit to the DRAM a first code to indicate that first data is to be written to the DRAM. The first code is to be sampled by the DRAM and held by the DRAM for a first period of time before it is issued inside the DRAM. The interface is further to transmit the first data that is to be sampled by the DRAM after a second period of time has elapsed from when the first code is sampled by the DRAM. The interface is further to transmit a second code, different from the first code, to indicate that second data is to be read from the DRAM. The second code is to be sampled by the DRAM on one or more edges of the external clock signal.
摘要翻译：一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括用于向DRAM发送第一代码以指示要将第一数据写入DRAM的接口。第一代码将由DRAM采样并由DRAM在DRAM发出之前的第一时间段内保持。该接口在从DRAM的第一代码被采样起经过了第二时间段之后，进一步发送由DRAM采样的第一数据。该接口还用于发送与第一代码不同的第二代码，以指示要从DRAM读取第二数据。第二个代码由外部时钟信号的一个或多个边缘上的DRAM采样。

7. 发明授权

US08214616B2 Memory controller device having timing offset capability 有权
标题翻译：具有定时偏移能力的存储器控制器装置
公开(公告)号：US08214616B2
公开(公告)日：2012-07-03
申请号：US11754995
申请日：2007-05-29
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F13/36
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset such that the first data arrives at a first memory device in accordance with a predetermined timing relationship with respect to a first transition of the clock signal, and a third transmitter to output second data suing a second timing offset such that the second data arrives at a second memory device in accordance with a predetermined timing relationship with respect to a second transition of the clock signal.
摘要翻译：公开了一种存储器控制器。在一个特定的示例性实施例中，存储器控制器可以包括：第一发射器，用于相对于时钟信号同步地输出第一和第二写入命令;第二发射器，使用第一定时偏移来输出第一数据，使得第一数据到达第一根据与时钟信号的第一次转换相关的预定定时关系，存储器件;以及第三发送器，输出第二数据，该第二数据产生第二定时偏置，使得第二数据按照预定定时到达第二存储器件关于时钟信号的第二转换。

8. 发明授权

US08195907B2 Timing adjustment in a reconfigurable system 有权
标题翻译：可重构系统中的时序调整
公开(公告)号：US08195907B2
公开(公告)日：2012-06-05
申请号：US12258680
申请日：2008-10-27
申请人： Frederick A. Ware , Ian Shaeffer , Scott C. Best , Craig E. Hampel
发明人： Frederick A. Ware , Ian Shaeffer , Scott C. Best , Craig E. Hampel
IPC分类号： G06F1/08 , G06F13/16
CPC分类号： G06F13/4243
摘要： This disclosure provides a method for adjusting system timing in a reconfigurable memory system. In a Dynamic Point-to-Point (“DPP”) system, for example, manufacturer-supplied system timing parameters such as access latency and maximum clock speed typically reflect a worst-case configuration scenario. By in-situ detecting actual configuration (e.g., whether expansion boards have been inserted), and correspondingly configuring the system to operate in a mode geared to the specific configuration, worst-case or near worst-case scenarios may be ruled out and system timing parameters may be redefined for faster-than-conventionally-rated performance; this is especially the case in a DPP system where signal pathways typically become more direct as additional modules are added. Contrary to convention wisdom therefore, which might dictate that component expansion should slow down timing, clock speed can actually be increased in such a system, if supported by the configuration, for better performance.
摘要翻译：本公开提供了一种用于在可重构存储器系统中调整系统定时的方法。在动态点对点（“DPP”）系统中，例如，制造商提供的系统定时参数，例如访问延迟和最大时钟速度通常反映最坏情况的配置方案。通过原位检测实际配置（例如，是否插入了扩展板），并且相应地将系统配置为以特定配置的方式运行，可能排除最坏情况或接近最坏情况的情况，系统时序可以重新定义参数以达到比常规级别更高的性能; DPP系统尤其如此，其中信号路径通常随着附加模块的添加而变得更直接。因此，与惯例智慧相反，这可能决定组件扩展应该减慢时序，如果配置支持，这样的系统实际上可以增加时钟速度，以获得更好的性能。

9. 发明授权

US08112608B2 Variable-width memory 有权
标题翻译：可变宽度内存
公开(公告)号：US08112608B2
公开(公告)日：2012-02-07
申请号：US12631614
申请日：2009-12-04
申请人： Richard E Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Richard E Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F12/08
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.
摘要翻译：描述了存储器系统，其中存储器核心组织随设备宽度而变化。所访问的物理存储器组的数量随着器件宽度而减少，导致相对较窄的存储器配置的功率消耗减少。增加用于窄内存宽度的逻辑内存库的数量可以减少存储体冲突的可能性，从而提高速度性能。

10. 发明申请

US20110317465A1 Methods and Systems for Reducing Heat Flux in Memory Systems 有权
标题翻译：记忆系统中减少热通量的方法和系统
公开(公告)号：US20110317465A1
公开(公告)日：2011-12-29
申请号：US13224251
申请日：2011-09-01
申请人： Steven C. Woo , Craig E. Hampel
发明人： Steven C. Woo , Craig E. Hampel
IPC分类号： G11C5/06
CPC分类号： G11C5/02
摘要： The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits to a data bus. A second control line serially connects a second group of devices on both the front and back faces so that the second group of devices commonly contribute multiple bits to a data bus.
摘要翻译：内存模块包括前面和后面。在每个面上设置多个装置。第一控制线串联连接前面和后表面上的第一组设备，使得第一组设备通常向数据总线贡献多个位。第二控制线串联连接前面和后表面上的第二组设备，使得第二组设备通常向数据总线贡献多个位。

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