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1. 发明授权

US08331072B1 Timer controlled, short and open circuit fault detection with slew-rate boosted output driver 有权
标题翻译：定时器控制，短路和开路故障检测与转换速率提升输出驱动器
公开(公告)号：US08331072B1
公开(公告)日：2012-12-11
申请号：US12868652
申请日：2010-08-25
申请人： Huibo Liu , David Castaneda , Yuanfang Li
发明人： Huibo Liu , David Castaneda , Yuanfang Li
IPC分类号： H02H9/02
CPC分类号： H03F3/3022 , H03F1/52 , H03F3/45475 , H03F2203/45248
摘要： A driver circuit uses a feedback loop having a programmable timer and timer logic to adjust a slew rate delay period used to accommodate slewing current when charging or discharging a load capacitor, and to increase the current limit during the slew rate delay period by selecting a larger input current reference value. Increasing the current limit provides for a faster settling time. The value of each input current reference value can be programmed. The programmable timer and the timer logic can be configured to coordinate the slew rate delay period and the selected input current reference value. The slew rate delay period can be adjusted based on which input current reference value is applied.
摘要翻译：驱动器电路使用具有可编程定时器和定时器逻辑的反馈回路来调整用于在对负载电容器充电或放电时适应回转电流的转换速率延迟周期，并且通过选择更大的电压来增加转换速率延迟周期期间的电流限制输入电流参考值。增加电流限制提供更快的建立时间。每个输入电流参考值的值可编程。可编程定时器和定时器逻辑可以配置为协调转换速率延迟周期和所选输入电流参考值。可以根据应用哪个输入电流参考值来调整转换速率延迟周期。

2. 发明申请

US20120200442A1 PRECISION SUB-RADIX2 DAC WITH LINEARITY CALIBRATION 有权
标题翻译：精密子RADIX2 DAC，具有线性校准
公开(公告)号：US20120200442A1
公开(公告)日：2012-08-09
申请号：US13023093
申请日：2011-02-08
申请人： Yuanfang Li , David Castaneda , Daniel Alexander
发明人： Yuanfang Li , David Castaneda , Daniel Alexander
IPC分类号： H03M1/78
CPC分类号： H03M1/0692 , H03M1/1061 , H03M1/687 , H03M1/785
摘要： A system includes an N bit sub-binary radix digital-to-analog converter (DAC) that converts an m bit digital input signal to an analog output signal, where m and N are integers greater than or equal to 1 and N>m. A radix conversion module determines a code ratio, the code ratio being a ratio of a total number of available monotonic codes to 2m, and performs radix conversion on the m bit digital input signal based on the code ratio.
摘要翻译：一种系统包括将m位数字输入信号转换为模拟输出信号的N位二进制二进制数模转换器（DAC），其中m和N是大于或等于1且N> m的整数。基数转换模块确定码比，码比是可用单调码的总数与2m的比率，并且基于码比对m比特数字输入信号执行基数转换。

3. 发明授权

US08330634B2 Precision sub-radix2 DAC with linearity calibration 有权
标题翻译：精密sub-radix2 DAC，线性校准
公开(公告)号：US08330634B2
公开(公告)日：2012-12-11
申请号：US13023093
申请日：2011-02-08
申请人： Yuanfang Li , David Castaneda , Daniel Alexander
发明人： Yuanfang Li , David Castaneda , Daniel Alexander
IPC分类号： H03M1/78
CPC分类号： H03M1/0692 , H03M1/1061 , H03M1/687 , H03M1/785
摘要： A system includes an N bit sub-binary radix digital-to-analog converter (DAC) that converts an m bit digital input signal to an analog output signal, where m and N are integers greater than or equal to 1 and N>m. A radix conversion module determines a code ratio, the code ratio being a ratio of a total number of available monotonic codes to 2m, and performs radix conversion on the m bit digital input signal based on the code ratio.
摘要翻译：一种系统包括将m位数字输入信号转换为模拟输出信号的N位二进制二进制数模转换器（DAC），其中m和N是大于或等于1且N> m的整数。基数转换模块确定码比，码比是可用单调码的总数与2m的比率，并且基于码比对m比特数字输入信号执行基数转换。

4. 发明授权

US08581766B1 DAC with novel switch regulation 有权
标题翻译： DAC具有新颖的开关调节功能
公开(公告)号：US08581766B1
公开(公告)日：2013-11-12
申请号：US13351570
申请日：2012-01-17
申请人： Yuanfang Li , David Castaneda , Ling Liu
发明人： Yuanfang Li , David Castaneda , Ling Liu
IPC分类号： H03M1/78
CPC分类号： H03M1/785
摘要： A system includes an NL bit digital to analog converter (DAC) ladder module having NL ladder resistors connected in parallel, NL series resistors connected in series between the NL ladder resistors, and a plurality of switches. NL is an integer greater than one. Adjacent pairs of the plurality of switches are connected in series with respective ones of the ladder resistors. On resistances of each of the plurality of switches are approximately equal. A switch control module provides a plurality of switch control signals to respective ones of the plurality of switches.
摘要翻译：一个系统包括具有并联的NL梯形电阻器的NL位数模转换器（DAC）梯形模块，NL梯形电阻器之间串联连接的NL串联电阻器和多个开关。 NL是大于1的整数。多个开关的相邻对与各个梯形电阻串联连接。多个开关中的每一个的电阻大致相等。开关控制模块向多个开关中的相应开关提供多个开关控制信号。

5. 发明授权

US07023230B1 Method for testing IDD at multiple voltages 失效
标题翻译：在多个电压下测试IDD的方法
公开(公告)号：US07023230B1
公开(公告)日：2006-04-04
申请号：US10700791
申请日：2003-11-03
申请人： Ernest Allen, III , David Castaneda
发明人： Ernest Allen, III , David Castaneda
IPC分类号： G01R31/02
CPC分类号： G01R31/3008
摘要： According to one embodiment, a method of testing an integrated circuit is provided. The quiescent current measuring of an integrated circuit is measured at two voltages. The functional relationship between the current measurements is determined and compared against a predetermined functional relationship to determine whether a defect exists in the integrated circuit.
摘要翻译：根据一个实施例，提供一种测试集成电路的方法。在两个电压下测量集成电路的静态电流测量。确定电流测量之间的功能关系并将其与预定的功能关系进行比较，以确定集成电路中是否存在缺陷。

6. 发明授权

US06939727B1 Method for performing statistical post processing in semiconductor manufacturing using ID cells 失效
标题翻译：在使用ID单元的半导体制造中执行统计后处理的方法
公开(公告)号：US06939727B1
公开(公告)日：2005-09-06
申请号：US10701328
申请日：2003-11-03
申请人： Ernest Allen, III , David Castaneda , Miaw Looi
发明人： Ernest Allen, III , David Castaneda , Miaw Looi
IPC分类号： H01L21/66 , H01L23/544 , H01L31/26
CPC分类号： H01L22/20 , H01L22/34 , H01L2223/5448
摘要： A method of manufacturing a semiconductor integrated circuit includes providing a fabricated integrated circuit on a wafer. A test fixture is connected to unencapsulated pads on the integrated circuit to monitor an operating parameter for the circuit and to determine a unique identifier for the die. The parameter is analyzed in post processing.
摘要翻译：制造半导体集成电路的方法包括在晶片上提供制造的集成电路。测试夹具连接到集成电路上的未封装的焊盘，以监视电路的工作参数并确定芯片的唯一标识符。在后处理中分析参数。

7. 发明授权

US06642867B1 Replica compensated heterogeneous DACs and methods 有权
标题翻译：复制补偿异构DAC和方法
公开(公告)号：US06642867B1
公开(公告)日：2003-11-04
申请号：US10188897
申请日：2002-07-03
申请人： Rahim Chowdhury , Bo Yang , David Castaneda
发明人： Rahim Chowdhury , Bo Yang , David Castaneda
IPC分类号： H03M106
CPC分类号： H03M1/0678 , H03M1/687 , H03M1/747 , H03M1/785
摘要： Digital to analog converters having a hybrid two-stage structure. The first stage is a differential segmented current DAC controlled by the MSBs (most significant bits) of input data. The second stage is a resistor string DAC controlled by the LSBs (least significant bits) of the input data to interpolate between the differential outputs of the first stage. The resistor string is directly connected to the current DAC without the need of buffer amplifiers. Instead, a replica circuit is used to prevent the second-stage resistor string from loading the first stage current DAC. Compensation techniques are described.
摘要翻译：具有混合两级结构的数模转换器。第一级是由MSB（最高有效位）输入数据控制的差分分段电流DAC。第二级是由输入数据的LSB（最低有效位）控制的电阻串DAC，以在第一级的差分输出之间插值。电阻串直接连接到电流DAC而不需要缓冲放大器。而是使用复制电路来防止第二级电阻串加载第一级电流DAC。描述了补偿技术。

8. 发明授权

US06266001B1 Method and apparatus for switching low voltage CMOS switches in high voltage digital to analog converters 有权
标题翻译：用于在高压数模转换器中切换低压CMOS开关的方法和装置
公开(公告)号：US06266001B1
公开(公告)日：2001-07-24
申请号：US09305908
申请日：1999-05-05
申请人： Gary G. Fang , David Castaneda , Chowdhury F. Rahim
发明人： Gary G. Fang , David Castaneda , Chowdhury F. Rahim
IPC分类号： H03M166
CPC分类号： H03M1/06 , H03M1/785
摘要： A varying power supply range, that can exceed the breakdown voltage of switches within a DAC, is used to generate positive and negative generated OFF voltages substantially fixed and less than the breakdown voltage to accommodate a wide range of analog reference voltages and power supply voltages. The digital input signal having digital input levels is received by a TTL/CMOS input receiver and level shifted to logic levels having the positive and negative generate voltage levels. A circuit matches switch resistance and forms positive and negative switch ON voltage levels from the voltage levels of the input positive and negative analog reference levels. Switch drivers properly drive control terminals of the switches with appropriate voltage levels avoiding switch breakdown in response to the digital input signal.
摘要翻译：可以使用可以超过DAC内的开关的击穿电压的变化的电源范围来产生基本上固定的并且小于击穿电压的正和负的产生的OFF电压，以适应宽范围的模拟参考电压和电源电压。具有数字输入电平的数字输入信号由TTL / CMOS输入接收器接收，电平转换为具有正和负产生电压电平的逻辑电平。电路匹配开关电阻，并从输入正模拟参考电平和负模拟参考电平的电压电平形成正负开关导通电压电平。开关驱动器正确地驱动开关的控制端子，具有适当的电压电平，避免了响应于数字输入信号的开关故障。

9. 发明授权

US06222473B1 Method and apparatus for digital to analog converters with improved switched R-2R ladders 有权
标题翻译：具有改进的开关R-2R梯形的数模转换器的方法和装置
公开(公告)号：US06222473B1
公开(公告)日：2001-04-24
申请号：US09299691
申请日：1999-04-26
申请人： David Castaneda , Gary G. Fang , Chowdhury F. Rahim
发明人： David Castaneda , Gary G. Fang , Chowdhury F. Rahim
IPC分类号： H03M178
CPC分类号： H03M1/06 , H03M1/785
摘要： Operating range of R-2R ladders for digital to analog converters (DACs) is improved by increasing resistance in series with a termination switch in a termination leg to avoid transistor saturation for increasing DAC resolution, increasing reference voltage range, or other application. The switched R-2R ladder circuit is modified to compensate for increasing resistance to maintain proper resistor matching for generation of the appropriate range of analog output voltages for a digital input signal.
摘要翻译：通过增加与终端脚中的终端开关串联的电阻来改善数模转换器（DAC）的R-2R级梯形图的工作范围，以避免晶体管饱和，从而提高DAC分辨率，增加参考电压范围或其他应用。修改了开关式R-2R梯形电路，以补偿增加的电阻，以保持适当的电阻匹配，以产生数字输入信号的适当范围的模拟输出电压。

10. 发明授权

US6154063A Class AB emitter follower buffers 有权
标题翻译： AB类射极跟随缓冲器
公开(公告)号：US6154063A
公开(公告)日：2000-11-28
申请号：US299359
申请日：1999-04-26
申请人： Gary G. Fang , David Castaneda , Chowdhury F. Rahim
发明人： Gary G. Fang , David Castaneda , Chowdhury F. Rahim
IPC分类号： H03F3/50 , H03K19/018
CPC分类号： H03F3/50
摘要： Buffers having an output pull-up transistor controlled by the input signal, an output pull-down transistor and a pull-down transistor control circuit. A current source provides a current that is divided between the pull-up transistor and the pull-down transistor control circuit to maintain the desired output voltage. A boost capacitor is coupled between the output and the pull-down transistor control circuit to provide good dynamic response to the circuit even in the presence of substantial capacitive loads on the output. In addition a second capacitor is coupled between the pull-down transistor control circuit and a fixed voltage to provide a low frequency pole internal to the circuit. The connection of the boost capacitor to the pull-down transistor control circuit and the connection of the second capacitor to the pull-down transistor control circuit are separated by a substantial resistance, allowing the effect of each capacitor to be substantially independent of each other. Exemplary circuits are disclosed incorporating these and other features.
摘要翻译：具有由输入信号控制的输出上拉晶体管的缓冲器，输出下拉晶体管和下拉晶体管控制电路。电流源提供在上拉晶体管和下拉晶体管控制电路之间划分的电流，以保持所需的输出电压。升压电容器耦合在输出和下拉晶体管控制电路之间，以便即使在输出上存在大量的电容性负载的情况下也能为电路提供良好的动态响应。此外，第二电容器耦合在下拉晶体管控制电路和固定电压之间以在电路内部提供低频极。升压电容器与下拉晶体管控制电路的连接以及第二电容器与下拉晶体管控制电路的连接被相当大的电阻分开，从而允许每个电容器的作用基本上彼此独立。公开了结合这些和其它特征的示例性电路。

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