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1. 发明授权

US08869007B2 Three dimensional (3D) memory device sparing 有权
标题翻译：三维（3D）存储设备备用
公开(公告)号：US08869007B2
公开(公告)日：2014-10-21
申请号：US13523091
申请日：2012-06-14
申请人： Edgar R. Cordero , Anil B. Lingambudi , Saravanan Sethuraman , Kenneth L. Wright
发明人： Edgar R. Cordero , Anil B. Lingambudi , Saravanan Sethuraman , Kenneth L. Wright
IPC分类号： G11C29/00 , G06F11/10 , G11C29/44 , H03M13/05
CPC分类号： G06F11/1072 , G06F11/1048 , G11C5/04 , G11C11/40 , G11C29/4401 , G11C29/886 , G11C2029/0409 , H03M13/05
摘要： According to one embodiment of the present invention, a method for operating a three dimensional (“3D”) memory device includes detecting, by a memory controller, a first error on the 3D memory device and detecting, by the memory controller, a second error in a first chip in a first rank of the 3D memory device, wherein the first chip has an associated first chip select. The method also includes powering up a second chip in a second rank, sending a command from the memory controller to the 3D memory device to replace the first chip in the first chip select with the second chip and correcting the first error using an error control code.
摘要翻译：根据本发明的一个实施例，一种用于操作三维（“3D”）存储器件的方法包括由存储器控制器检测3D存储器件上的第一个错误，并由存储器控制器检测第二个错误在3D存储器件的第一级中的第一芯片中，其中第一芯片具有相关的第一芯片选择。该方法还包括对第二级别的第二芯片供电，从存储器控制器向3D存储器件发送命令以将第一芯片中的第一芯片替换为第二芯片，并使用错误控制代码校正第一错误。

2. 发明申请

US20140063987A1 MEMORY OPERATION UPON FAILURE OF ONE OF TWO PAIRED MEMORY DEVICES 有权
公开(公告)号：US20140063987A1
公开(公告)日：2014-03-06
申请号：US13597926
申请日：2012-08-29
申请人： Edgar R. Cordero , Timothy J. Dell , Girisankar Paulraj , Saravanan Sethuraman
发明人： Edgar R. Cordero , Timothy J. Dell , Girisankar Paulraj , Saravanan Sethuraman
IPC分类号： G11C7/00
CPC分类号： G11C29/04 , G06F13/1673 , G11C29/70 , G11C29/808 , G11C2029/0411
摘要： A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.

3. 发明授权

US08552291B2 Cable for high speed data communications 失效
标题翻译：电缆用于高速数据通信
公开(公告)号：US08552291B2
公开(公告)日：2013-10-08
申请号：US12786673
申请日：2010-05-25
申请人： Anil B. Lingambudi , Bhyrav M. Mutnury , Nam H. Pham , Saravanan Sethuraman
发明人： Anil B. Lingambudi , Bhyrav M. Mutnury , Nam H. Pham , Saravanan Sethuraman
IPC分类号： H01B11/02
CPC分类号： H01B11/203 , H01B11/183
摘要： A cable for high speed data communications that includes a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer. The inner conductors and the dielectric layers are disposed within the cable in parallel with a longitudinal axis of the cable. The cable also includes drain conductors disposed within the cable laterally to the inner conductors adjacent to the dielectric layers along the longitudinal axis of the cable and within thirty degrees of a horizontal axis through the inner conductors. The cable also includes a conductive shield composed of a strip of conductive shield material wrapped in a rotational direction along and about the longitudinal axis around the inner conductors, the dielectric layers, and the drain conductors.
摘要翻译：一种用于高速数据通信的电缆，包括由第一电介质层包围的第一内导体和由第二电介质层包围的第二内导体。内部导体和电介质层与电缆的纵向轴线平行地布置在电缆内。电缆还包括设置在电缆内的漏极导体，沿着电缆的纵向轴线横向延伸到与电介质层相邻的内部导体，并且在穿过内部导体的水平轴线的30度内。电缆还包括导电屏蔽，该导电屏蔽由导电屏蔽材料条构成，沿着围绕内部导体，电介质层和漏极导体的纵轴围绕旋转方向缠绕。

4. 发明申请

US20110302481A1 Translation Between A First Communication Protocol And A Second Communication Protocol 失效
标题翻译：第一个通信协议和第二个通信协议之间的翻译
公开(公告)号：US20110302481A1
公开(公告)日：2011-12-08
申请号：US13150486
申请日：2011-06-01
申请人： Jean L. Calvignac , Daniel G. Eisenhauer , Ashish A. More , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann
发明人： Jean L. Calvignac , Daniel G. Eisenhauer , Ashish A. More , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann
IPC分类号： H04J3/22 , G06F11/10 , H03M13/09
CPC分类号： H04L69/08 , H03M13/09
摘要： Translating between a first communication protocol used by a first network component and a second communication protocol used by a second network, where translating includes: receiving, by a network engine adapter operating independently from the first and second network components, data packets from the first and second network components; and performing, by the network engine, a combined communication protocol based on the first communication protocol and the second communication protocol, including manipulating data packets of at least one of the first communication protocol or the second communication protocol, thereby offloading performance requirements for the combined communication protocol from the first and second network components.
摘要翻译：在由第一网络组件使用的第一通信协议和由第二网络使用的第二通信协议之间进行翻译，其中转换包括：由独立于第一和第二网络组件的网络引擎适配器接收来自第一和第二网络组件的数据分组第二网络组件; 以及由网络引擎执行基于第一通信协议和第二通信协议的组合通信协议，包括操纵第一通信协议或第二通信协议中的至少一个的数据分组，由此卸载组合的性能要求来自第一和第二网络组件的通信协议。

5. 发明申请

US20080172604A1 TIME REDUCTION MECHANISM IN SCHEMATIC DESIGN ENTRY PAGE SETUP 审中-公开
标题翻译：时间减少机制在设计设计入门页面设置
公开(公告)号：US20080172604A1
公开(公告)日：2008-07-17
申请号：US11617602
申请日：2006-12-28
申请人： Saravanan Sethuraman
发明人： Saravanan Sethuraman
IPC分类号： G06F17/00 , G06F17/50
CPC分类号： G06F17/5045
摘要： A method and system for schematic design entry page setup are provided. In one aspect, the method may comprise presenting a user interface for entering information associated with a page layout for designing hardware logic schematics, retrieving the entered information and creating a specified number of pages for schematic design entry to automatically include the entered information on the pages. A system in one aspect may comprise a script operable to execute on a machine to present a user interface for entering information associated with a page layout for designing hardware logic schematics, the script further operable to retrieve the entered information. The system may also include means for creating a specified number of pages for schematic design entry to automatically include the entered information on the pages. An option to change and/or update information upfront without having to navigate to individual pages may be provided.
摘要翻译：提供了一种用于原理图设计入门页面设置的方法和系统。在一个方面，该方法可以包括呈现用于输入与用于设计硬件逻辑示意图的页面布局相关联的信息的用户界面，检索输入的信息并创建用于原理图设计输入的指定数目的页面以在页面上自动地包括输入的信息。一个方面中的系统可以包括可操作以在机器上执行的脚本，以呈现用于输入与用于设计硬件逻辑示意图的页面布局相关联的信息的用户界面，该脚本还可操作以检索输入的信息。该系统还可以包括用于为原理图设计输入创建指定数量的页面以自动将输入的信息包括在页面上的装置。可以提供改变和/或更新信息而不必导航到各个页面的选项。

6. 发明授权

US08676559B2 System and method for providing efficient schematic review 失效
标题翻译：提供高效示意图的系统和方法
公开(公告)号：US08676559B2
公开(公告)日：2014-03-18
申请号：US12566509
申请日：2009-09-24
申请人： Saravanan Sethuraman , John Francis Mullen
发明人： Saravanan Sethuraman , John Francis Mullen
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A system and method for providing schematic reviews is provided. The method includes providing a schematic design, selecting a signal, where the signal is a graphical representation, previewing the signal, obtaining relevant information on components constituting the signal, and controlling the signal to obtain relevant information on the components. Controlling the signal comprises activating a link to a data compilation related to the signal component, and activating the data compilation comprises creating a link to a datasheet. The graphic representation of the signal comprises providing a block diagram overview of connectivity of the signal components and the graphical representation comprises a graphical three dimensional model, and providing a log database that includes review information provided by multiple reviewers and is accessible by the reviewers. A notation medium is provided for the reviewers for communication between the reviewers.
摘要翻译：提供了一种用于提供示意图评估的系统和方法。该方法包括提供示意性设计，选择信号，其中信号是图形表示，预览信号，获得关于组成信号的组件的相关信息，以及控制信号以获得关于组件的相关信息。控制信号包括激活与信号分量相关的数据汇编的链接，并且激活数据编译包括创建到数据表的链接。信号的图形表示包括提供信号分量的连接性的框图，图形表示包括图形三维模型，以及提供包括由多个审阅者提供的审阅信息并且可由审阅者访问的日志数据库。为审阅者提供了一种记录介质，用于审阅者之间的通信。

7. 发明申请

US20120007875A1 Multiple Monitor Video Control 审中-公开
标题翻译：多监视器视频控制
公开(公告)号：US20120007875A1
公开(公告)日：2012-01-12
申请号：US12834129
申请日：2010-07-12
申请人： Saravanan Sethuraman , Sreekrishnan Venkiteswaran
发明人： Saravanan Sethuraman , Sreekrishnan Venkiteswaran
IPC分类号： G09G5/36
CPC分类号： G06F3/1431
摘要： A computer system comprising a processor including a display controller operative to output display data and a clock signal, and a programmable logic device communicatively connected to the processor, the programmable logic device including a first FIFO (first in first out) module operative to receive display data from the display controller and output display data to a display device, a second FIFO module, a scaler module communicatively connected to the first FIFO module and the second FIFO module operative to scale the display data received from the first FIFO module and output the scaled display data to the second FIFO module, and a synchronization generator operative to receive the clock signal from the display controller and to control the first FIFO and the second FIFO.
摘要翻译：一种包括处理器的计算机系统，所述处理器包括可操作以输出显示数据和时钟信号的显示控制器，以及通信地连接到所述处理器的可编程逻辑设备，所述可编程逻辑设备包括第一FIFO（先进先出）模块，来自显示控制器的数据和输出显示数据到显示设备，第二FIFO模块，通信地连接到第一FIFO模块的定标器模块和第二FIFO模块，其可操作以缩放从第一FIFO模块接收的显示数据，并输出缩放向第二FIFO模块显示数据，以及同步发生器，用于从显示控制器接收时钟信号并控制第一FIFO和第二FIFO。

8. 发明授权

US07979823B2 Identification of voltage reference errors in PCB designs 有权
标题翻译：识别PCB设计中的电压参考误差
公开(公告)号：US07979823B2
公开(公告)日：2011-07-12
申请号：US12193119
申请日：2008-08-18
申请人： Anil Bindu Lingambudi , Saravanan Sethuraman , Anandavally Sreekala
发明人： Anil Bindu Lingambudi , Saravanan Sethuraman , Anandavally Sreekala
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Disclosed is a computer implemented method for determining a voltage reference error in a PCB design comprising receiving information about said PCB design, identifying a signal associated with said design, receiving one or more user defined voltage references for said signal, and comparing the user defined voltage reference to the voltages of the power planes adjacent to said signal.
摘要翻译：公开了一种用于确定PCB设计中的电压参考误差的计算机实现方法，包括接收关于所述PCB设计的信息，识别与所述设计相关联的信号，接收用于所述信号的一个或多个用户定义的电压参考，以及将用户定义的电压参考与所述信号相邻的电力平面的电压。

9. 发明申请

US20090150834A1 METHOD OF REUSING CONSTRAINTS IN PCB DESIGNS 失效
标题翻译：在PCB设计中重新制约约束的方法
公开(公告)号：US20090150834A1
公开(公告)日：2009-06-11
申请号：US11954092
申请日：2007-12-11
申请人： Anil Bindu Lingambudi , Ankur Kanu Patel , Saravanan Sethuraman , Diyanesh Vidyapoornachary Babu Chinnakkonda
发明人： Anil Bindu Lingambudi , Ankur Kanu Patel , Saravanan Sethuraman , Diyanesh Vidyapoornachary Babu Chinnakkonda
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method is disclosed for electronically processing constraints rules defined in a previously developed first PCB design having a first constraints output file, to facilitate the development of a second PCB design having a second constraints output file. The second design has substantially identical topology to the first design and the second constraints output file comprises constraints for signals with identical attributes. The method includes several steps. Firstly, the board file of the first design is compared with the net list file of the second design to identify respective differences between the designs. On the basis of the established differences, a file attributes change report is generated. At least some data from the file attributes change report is stored into an attributes change file. Finally, the method includes the step of processing the first design constraints output file, the second design constraints output file, and the attribute change file to map constraints associated with changed attributes, thus defining a revised constraints output file for the second design. The revised second constraints output file comprises constraints for at least some signals with changed attributes.
摘要翻译：公开了一种用于电子处理在先前开发的具有第一约束输出文件的第一PCB设计中定义的约束规则的方法，以便于开发具有第二约束输出文件的第二PCB设计。第二设计具有与第一设计基本相同的拓扑，第二约束输出文件包括具有相同属性的信号的约束。该方法包括几个步骤。首先，将第一设计的板文件与第二设计的网表文件进行比较，以识别设计之间的差异。在建立的差异的基础上，生成文件属性变更报告。文件属性更改报告中的至少一些数据将存储到属性更改文件中。最后，该方法包括处理第一设计约束输出文件，第二设计约束输出文件和属性更改文件以映射与改变的属性相关联的约束的步骤，从而为第二设计定义修改的约束输出文件。修改的第二约束输出文件包括至少一些具有变化属性的信号的约束。

10. 发明授权

US08848470B2 Memory operation upon failure of one of two paired memory devices 有权
标题翻译：两个成对存储器件之一故障时的存储器操作
公开(公告)号：US08848470B2
公开(公告)日：2014-09-30
申请号：US13597926
申请日：2012-08-29
申请人： Edgar R. Cordero , Timothy J. Dell , Girisankar Paulraj , Saravanan Sethuraman
发明人： Edgar R. Cordero , Timothy J. Dell , Girisankar Paulraj , Saravanan Sethuraman
IPC分类号： G11C29/00
CPC分类号： G11C29/04 , G06F13/1673 , G11C29/70 , G11C29/808 , G11C2029/0411
摘要： A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.
摘要翻译：一种当存储器件之一失败时，用于继续操作包括第一和第二存储器件的存储器模块的方法和装置。该方法包括：通过第一存储器模块接收写入操作请求以写入具有第一和第二部分的数据字。存储器模块可以具有用于分别存储数据字的第一和第二部分的第一存储器设备和第二存储器设备。确定第一和第二存储器件之一是否不可操作。如果第一和第二存储器件之一不能操作，则通过将数据字的第一和第二部分写入第一和第二存储器件中的可操作的一个来执行写入操作。

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