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1. 发明授权

US6134633A Prefetch management in cache memory 失效
标题翻译：缓存中的预取管理
公开(公告)号：US6134633A
公开(公告)日：2000-10-17
申请号：US961963
申请日：1997-10-31
申请人： Eino Jacobs
发明人： Eino Jacobs
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F12/0862 , G06F9/383
摘要： A computer system, a cache memory and a process, supporting prefetch operations and cache access operations so as to store information duplicated from a high level memory for use by a processing device, the processing device issuing addresses, including prefetch addresses and cache access addresses. The cache memory comprises memory resources, and prefetch resources are coupled to the memory resources and to the processing device both for receipt and storage of prefetch addresses from the processing device and for injection management of the received prefetch addresses so as to coordinate prefetch operations with cache access operations. As for the process, the invention comprises the steps of receiving prefetch addresses issued by a processing device; providing for storing, in a prefetch memory, prefetch addresses; and providing for injecting prefetch addresses in a selected order from the prefetch memory for use in fetching, into the cache memory, information associated with the prefetch addresses.
摘要翻译：一种计算机系统，高速缓冲存储器和处理，支持预取操作和高速缓存存取操作，以便存储从处理设备使用的高级存储器中复制的信息，处理设备发布地址，包括预取地址和高速缓存存取地址。高速缓存存储器包括存储器资源，并且预取资源被耦合到存储器资源和处理设备，用于从处理设备接收和存储预取地址，并且用于注入管理所接收的预取地址，以便将预取操作与高速缓存访问操作。对于该过程，本发明包括以下步骤：接收由处理设备发出的预取地址; 提供在预取存储器中存储预取地址; 并且提供从预取存储器中以选定的顺序注入预取地址，以用于将高速缓冲存储器提取与预取地址相关联的信息。

2. 发明授权

US5826054A Compressed Instruction format for use in a VLIW processor 失效
标题翻译：用于VLIW处理器的压缩指令格式
公开(公告)号：US5826054A
公开(公告)日：1998-10-20
申请号：US649733
申请日：1996-05-15
申请人： Eino Jacobs , Michael Ang
发明人： Eino Jacobs , Michael Ang
IPC分类号： G06F9/30 , G06F9/38 , G06F12/04 , G06F9/22 , H03M7/30
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30156 , G06F9/30167 , G06F9/3822
摘要： A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
摘要翻译：用于VLIW处理器的压缩指令格式允许更高的使用高速缓存和存储器的效率。指令是字节对齐和可变长度。分支目标未压缩。格式位指定在以下指令中使用多少个问题槽。 NOPS不存储在内存中。个别操作根据特征进行压缩，例如是否无结果，守卫，简短，零，一元或二进制。指令以压缩形式存储在内存和缓存中。从高速缓存中读出指令后即可解除指令。

3. 发明授权

US6131152A Planar cache layout and instruction stream therefor 失效
标题翻译：平面缓存布局和指令流
公开(公告)号：US6131152A
公开(公告)日：2000-10-10
申请号：US648333
申请日：1996-05-15
申请人： Michael Ang , Eino Jacobs
发明人： Michael Ang , Eino Jacobs
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0895
摘要： Cache layout is simplified by swizzling the bits of instruction words. Then the words are read out of cache by using a shuffled bit stream which simplifies cache layout. The object is further met using a cache structure which includes a device for storing a shuffled instruction stream; and a device for multiplexing bits from the storage means onto the bus so that the bits are deshuffled. The multiplexing means includes a multiplicity of lines leading from the storage device to the bus. The read lines do not cross each other.
摘要翻译：通过旋转指令字的位来简化缓存布局。然后通过使用简化缓存布局的混洗位流读出高速缓存。使用包括用于存储混洗指令流的设备的缓存结构进一步满足该对象; 以及用于将来自存储装置的比特复用到总线上以使得比特被去混洗的装置。多路复用装置包括从存储装置引导到总线的多条线路。读取行不会相互交叉。

4. 发明授权

US6047358A Computer system, cache memory and process for cache entry replacement with selective locking of elements in different ways and groups 失效
标题翻译：计算机系统，高速缓冲存储器和缓存条目替换的过程，以不同的方式和组对元素进行选择性锁定
公开(公告)号：US6047358A
公开(公告)日：2000-04-04
申请号：US961965
申请日：1997-10-31
申请人： Eino Jacobs
发明人： Eino Jacobs
IPC分类号： G06F12/08 , G06F12/12 , G06F13/00
CPC分类号： G06F12/126
摘要： A computer system, a cache memory and a process, each enabling a cache replacement policy with locking. The computer system comprises a processing device and a memory system, the memory system including a higher level memory, a cache memory and lock ordering resources. The higher level memory provides for storage of information and the cache memory duplicates certain of that information in cache blocks, the cache memory comprising elements organized in sets and ways, wherein each cache block can reside in any element of a set to which the cache block is assigned, and includes a replacement policy. The lock ordering resources is capable of utilizing a granularity of less than an entire way and a selected contiguity of element locking proceeding through selected ways, element-by-element, in a selected order starting from a selected beginning element of one of the selected ways. The lock ordering resources may include a sequencer, a cache control, a first storage device for storing an address of a first cache block to be locked, and a second storage device storing the number of elements for locking. The lock ordering resources may also include a lock vector administrator and a least recently used (LRU) administrator. Cache blocks having addresses in a lock range may be loaded into elements of the selected ways.
摘要翻译：计算机系统，高速缓冲存储器和进程，每个启用具有锁定的高速缓存替换策略。计算机系统包括处理装置和存储器系统，所述存储器系统包括较高级存储器，高速缓冲存储器和锁定排序资源。高级存储器提供信息的存储，并且高速缓存存储器在高速缓存块中复制该信息中的某些信息，高速缓冲存储器包括以组和方式组织的元件，其中每个高速缓存块可以驻留在高速缓存块被分配，并且包括替换策略。锁定排序资源能够利用小于整个方式的粒度，并且以所选择的顺序从所选择的一种方式的所选择的起始元素开始，通过选择的方式逐个元素地执行元素锁定的选择的邻接性。锁排序资源可以包括定序器，高速缓存控制，用于存储要锁定的第一高速缓存块的地址的第一存储设备，以及存储用于锁定的元素数量的第二存储设备。锁定排序资源还可以包括锁定向量管理员和最近最少使用的（LRU）管理员。具有锁定范围内的地址的缓存块可以被加载到所选择的方式的元素中。

5. 发明授权

US5862398A Compiler generating swizzled instructions usable in a simplified cache layout 失效
标题翻译：编译器生成可在简化的缓存布局中使用的转换指令
公开(公告)号：US5862398A
公开(公告)日：1999-01-19
申请号：US649732
申请日：1996-05-15
申请人： Hari Hampapuram , Yen C. Lee , Michael Ang , Eino Jacobs
发明人： Hari Hampapuram , Yen C. Lee , Michael Ang , Eino Jacobs
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0895
摘要： The software which produces a shuffled bit stream which bit stream allows for a simplified cache layout. This object is met using computer software which includes code for receiving a compiled and linked object module produced by a compiler and/or linker and code for swizzling the compiled and linked software to produce a second object module. The second object module is suitable for being deswizzled upon reading from a cache memory using a cache structure whose output bus wires are not crossed.
摘要翻译：产生混洗位流的软件，其位流允许简化的缓存布局。使用计算机软件来满足该对象，所述计算机软件包括用于接收由编译器和/或链接器产生的编译和链接的对象模块的代码以及用于对所编译和链接的软件进行转换以产生第二对象模块的代码。第二对象模块适用于使用其输出总线未被交叉的高速缓存结构从高速缓冲存储器读取时被解散。

6. 发明授权

US06704859B1 Compressed instruction format for use in a VLIW processor 有权
标题翻译：用于VLIW处理器的压缩指令格式
公开(公告)号：US06704859B1
公开(公告)日：2004-03-09
申请号：US09128832
申请日：1998-08-04
申请人： Eino Jacobs , Michael Ang
发明人： Eino Jacobs , Michael Ang
IPC分类号： G06F900
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30156 , G06F9/30167 , G06F9/3822
摘要： A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
摘要翻译：用于VLIW处理器的压缩指令格式允许更高的使用高速缓存和存储器的效率。指令是字节对齐和可变长度。分支目标未压缩。格式位指定在以下指令中使用多少个问题槽。 NOPS不存储在内存中。个别操作根据特征进行压缩，例如是否无结果，守卫，简短，零，一元或二进制。指令以压缩形式存储在内存和缓存中。从高速缓存中读出指令后即可解除指令。

7. 发明授权

US06385678B2 Method and apparatus for bus arbitration with weighted bandwidth allocation 失效
标题翻译：具有加权带宽分配的总线仲裁的方法和装置
公开(公告)号：US06385678B2
公开(公告)日：2002-05-07
申请号：US08715946
申请日：1996-09-19
申请人： Eino Jacobs , Tzungren Tzeng
发明人： Eino Jacobs , Tzungren Tzeng
IPC分类号： G06F1336
CPC分类号： G06F13/364
摘要： A method and apparatus for bus arbitration wherein each bus agent is assigned a weight that governs the percentage of bandwidth allocated to the agent. In addition, each bus agent may also raise the priority of its request based on the amount of time that agent's request has not been serviced. Specifically, the waiting period for the agent is selected so that the agent would be guaranteed access to the bus such that a worst case latency constraint is satisfied. Finally, the arbitration scheme of the present invention can be split into multiple levels of hierarchy, such that when an agent wins arbitration at one level, it is passed to the next higher level where it competes with other agents for bus access.
摘要翻译：一种用于总线仲裁的方法和装置，其中为总线代理分配一个控制分配给代理的带宽百分比的权重。此外，每个总线代理还可以基于代理的请求未被服务的时间量来提高其请求的优先级。特别地，选择代理的等待时间，使得代理将被保证访问总线，使得满足最坏情况的延迟约束。最后，本发明的仲裁方案可以被分成多层次的层次结构，使得当一个代理人在一个级别获胜时，它被传递到下一个较高级别，在那里与其他代理商进行总线访问竞争。

8. 发明授权

US5909563A Computer system including an interface for transferring data between two clock domains 失效
标题翻译：计算机系统包括用于在两个时钟域之间传送数据的接口
公开(公告)号：US5909563A
公开(公告)日：1999-06-01
申请号：US914473
申请日：1997-08-19
申请人： Eino Jacobs
发明人： Eino Jacobs
IPC分类号： G06F13/42 , G06F1/12 , G06F9/30 , G06F13/40 , H04L7/00 , H04L7/02 , G06F13/38
CPC分类号： G06F9/30141 , G06F13/405 , H04L7/0012 , H04L7/02
摘要： An interface between two clock domains transfers data between the two clock domains without corruption or loss of data being transferred. Each clock domain has a respective clock. The two clocks have a fixed relationship. A data signal is registered in a plurality of registers in the first clock domain, the number of which is related to the fixed relationship of the clocks. Each register outputs a specific output signal, one of which is selected by a multiplexer in the second clock domain, to be output to an output register. The output register then outputs the data in synchronism with the second clock.
摘要翻译：两个时钟域之间的接口在两个时钟域之间传输数据，而不会损坏或丢失正在传输的数据。每个时钟域都有相应的时钟。两个时钟有固定的关系。数据信号被登记在第一时钟域中的多个寄存器中，其数量与时钟的固定关系相关。每个寄存器输出特定的输出信号，其中一个由第二个时钟域中的多路复用器选择，以输出到输出寄存器。输出寄存器然后与第二个时钟同步输出数据。

9. 发明授权

US5852741A VLIW processor which processes compressed instruction format 失效
标题翻译：处理压缩指令格式的VLIW处理器
公开(公告)号：US5852741A
公开(公告)日：1998-12-22
申请号：US648359
申请日：1996-05-15
申请人： Eino Jacobs , Michael Ang
发明人： Eino Jacobs , Michael Ang
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30156 , G06F9/30167 , G06F9/3822
摘要： A VLIW processor uses a compressed instruction format that allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
摘要翻译： VLIW处理器使用压缩指令格式，可以更高效地使用缓存和内存。指令是字节对齐和可变长度。分支目标未压缩。格式位指定在以下指令中使用多少个问题槽。 NOPS不存储在内存中。个别操作根据特征进行压缩，例如是否无结果，守卫，简短，零，一元或二进制。指令以压缩形式存储在内存和缓存中。从高速缓存中读出指令后即可解除指令。

10. 发明授权

US5931939A Read crossbar elimination in a VLIW processor 失效
标题翻译：在VLIW处理器中阅读交叉开关
公开(公告)号：US5931939A
公开(公告)日：1999-08-03
申请号：US909273
申请日：1997-08-11
申请人： Eino Jacobs
发明人： Eino Jacobs
IPC分类号： G06F9/30 , G06F9/38 , H04L7/00 , G06F9/34 , G06F9/44
CPC分类号： G06F9/30141 , G06F9/30167 , G06F9/3885 , H04L7/0012
摘要： In a VLIW processor that has an instruction issue register, functional units, and a multiport register file, a portion or all of the read crossbar is eliminated.
摘要翻译：在具有指令发布寄存器，功能单元和多端口寄存器文件的VLIW处理器中，消除了读取交叉开关的一部分或全部。

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