专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5826054A Compressed Instruction format for use in a VLIW processor 失效
标题翻译：用于VLIW处理器的压缩指令格式
公开(公告)号：US5826054A
公开(公告)日：1998-10-20
申请号：US649733
申请日：1996-05-15
申请人： Eino Jacobs , Michael Ang
发明人： Eino Jacobs , Michael Ang
IPC分类号： G06F9/30 , G06F9/38 , G06F12/04 , G06F9/22 , H03M7/30
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30156 , G06F9/30167 , G06F9/3822
摘要： A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
摘要翻译：用于VLIW处理器的压缩指令格式允许更高的使用高速缓存和存储器的效率。指令是字节对齐和可变长度。分支目标未压缩。格式位指定在以下指令中使用多少个问题槽。 NOPS不存储在内存中。个别操作根据特征进行压缩，例如是否无结果，守卫，简短，零，一元或二进制。指令以压缩形式存储在内存和缓存中。从高速缓存中读出指令后即可解除指令。

2. 发明授权

US08583895B2 Compressed instruction format for use in a VLIW processor 失效
标题翻译：用于VLIW处理器的压缩指令格式
公开(公告)号：US08583895B2
公开(公告)日：2013-11-12
申请号：US10762863
申请日：2004-01-22
申请人： Eino Jacobs , Michael Ang
发明人： Eino Jacobs , Michael Ang
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30156 , G06F9/30178 , G06F9/3816 , G06F9/3822 , G06F9/3885
摘要： A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
摘要翻译：用于VLIW处理器的压缩指令格式允许更高的使用高速缓存和存储器的效率。指令是字节对齐和可变长度。分支目标未压缩。格式位指定在以下指令中使用多少个问题槽。 NOPS不存储在内存中。个别操作根据特征进行压缩，例如是否无结果，守卫，简短，零，一元或二进制。指令以压缩形式存储在内存和缓存中。从高速缓存中读出指令后即可解除指令。

3. 发明授权

US5787302A Software for producing instructions in a compressed format for a VLIW processor 失效
标题翻译：用于以VLIW处理器的压缩格式生成指令的软件
公开(公告)号：US5787302A
公开(公告)日：1998-07-28
申请号：US649731
申请日：1996-05-15
申请人： Hari Hampapuram , Yen C. Lee , Eino Jacobs , Michael Ang
发明人： Hari Hampapuram , Yen C. Lee , Eino Jacobs , Michael Ang
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F7/00
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30156 , G06F9/30167 , G06F9/3822
摘要： Software creates a compressed instruction format for a VLIW processor which allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
摘要翻译：软件为VLIW处理器创建一个压缩指令格式，可以提高高速缓存和内存的使用效率。指令是字节对齐和可变长度。分支目标未压缩。格式位指定在以下指令中使用多少个问题槽。 NOPS不存储在内存中。个别操作根据特征进行压缩，例如是否无结果，守卫，简短，零，一元或二进制。指令以压缩形式存储在内存和缓存中。从高速缓存中读出指令后即可解除指令。

4. 发明授权

US5878267A Compressed instruction format for use in a VLIW processor and processor for processing such instructions 失效
标题翻译：用于VLIW处理器和处理器的压缩指令格式用于处理此类指令
公开(公告)号：US5878267A
公开(公告)日：1999-03-02
申请号：US86696
申请日：1998-05-29
申请人： Hari Hampapuram , Yen C Lee , Eino Jacobs , Michael Ang
发明人： Hari Hampapuram , Yen C Lee , Eino Jacobs , Michael Ang
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F7/00
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30156 , G06F9/30167 , G06F9/3822
摘要： Software creates a compressed instruction format for a VLIW processor which allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
摘要翻译：软件为VLIW处理器创建一个压缩指令格式，可以提高高速缓存和内存的使用效率。指令是字节对齐和可变长度。分支目标未压缩。格式位指定在以下指令中使用多少个问题槽。 NOPS不存储在内存中。个别操作根据特征进行压缩，例如是否无结果，守卫，简短，零，一元或二进制。指令以压缩形式存储在内存和缓存中。从高速缓存中读出指令后即可解除指令。

5. 发明授权

US6131152A Planar cache layout and instruction stream therefor 失效
标题翻译：平面缓存布局和指令流
公开(公告)号：US6131152A
公开(公告)日：2000-10-10
申请号：US648333
申请日：1996-05-15
申请人： Michael Ang , Eino Jacobs
发明人： Michael Ang , Eino Jacobs
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0895
摘要： Cache layout is simplified by swizzling the bits of instruction words. Then the words are read out of cache by using a shuffled bit stream which simplifies cache layout. The object is further met using a cache structure which includes a device for storing a shuffled instruction stream; and a device for multiplexing bits from the storage means onto the bus so that the bits are deshuffled. The multiplexing means includes a multiplicity of lines leading from the storage device to the bus. The read lines do not cross each other.
摘要翻译：通过旋转指令字的位来简化缓存布局。然后通过使用简化缓存布局的混洗位流读出高速缓存。使用包括用于存储混洗指令流的设备的缓存结构进一步满足该对象; 以及用于将来自存储装置的比特复用到总线上以使得比特被去混洗的装置。多路复用装置包括从存储装置引导到总线的多条线路。读取行不会相互交叉。

6. 发明授权

US5862398A Compiler generating swizzled instructions usable in a simplified cache layout 失效
标题翻译：编译器生成可在简化的缓存布局中使用的转换指令
公开(公告)号：US5862398A
公开(公告)日：1999-01-19
申请号：US649732
申请日：1996-05-15
申请人： Hari Hampapuram , Yen C. Lee , Michael Ang , Eino Jacobs
发明人： Hari Hampapuram , Yen C. Lee , Michael Ang , Eino Jacobs
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0895
摘要： The software which produces a shuffled bit stream which bit stream allows for a simplified cache layout. This object is met using computer software which includes code for receiving a compiled and linked object module produced by a compiler and/or linker and code for swizzling the compiled and linked software to produce a second object module. The second object module is suitable for being deswizzled upon reading from a cache memory using a cache structure whose output bus wires are not crossed.
摘要翻译：产生混洗位流的软件，其位流允许简化的缓存布局。使用计算机软件来满足该对象，所述计算机软件包括用于接收由编译器和/或链接器产生的编译和链接的对象模块的代码以及用于对所编译和链接的软件进行转换以产生第二对象模块的代码。第二对象模块适用于使用其输出总线未被交叉的高速缓存结构从高速缓冲存储器读取时被解散。

7. 发明授权

US06704859B1 Compressed instruction format for use in a VLIW processor 有权
标题翻译：用于VLIW处理器的压缩指令格式
公开(公告)号：US06704859B1
公开(公告)日：2004-03-09
申请号：US09128832
申请日：1998-08-04
申请人： Eino Jacobs , Michael Ang
发明人： Eino Jacobs , Michael Ang
IPC分类号： G06F900
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30156 , G06F9/30167 , G06F9/3822
摘要： A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
摘要翻译：用于VLIW处理器的压缩指令格式允许更高的使用高速缓存和存储器的效率。指令是字节对齐和可变长度。分支目标未压缩。格式位指定在以下指令中使用多少个问题槽。 NOPS不存储在内存中。个别操作根据特征进行压缩，例如是否无结果，守卫，简短，零，一元或二进制。指令以压缩形式存储在内存和缓存中。从高速缓存中读出指令后即可解除指令。

8. 发明授权

US5852741A VLIW processor which processes compressed instruction format 失效
标题翻译：处理压缩指令格式的VLIW处理器
公开(公告)号：US5852741A
公开(公告)日：1998-12-22
申请号：US648359
申请日：1996-05-15
申请人： Eino Jacobs , Michael Ang
发明人： Eino Jacobs , Michael Ang
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30156 , G06F9/30167 , G06F9/3822
摘要： A VLIW processor uses a compressed instruction format that allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
摘要翻译： VLIW处理器使用压缩指令格式，可以更高效地使用缓存和内存。指令是字节对齐和可变长度。分支目标未压缩。格式位指定在以下指令中使用多少个问题槽。 NOPS不存储在内存中。个别操作根据特征进行压缩，例如是否无结果，守卫，简短，零，一元或二进制。指令以压缩形式存储在内存和缓存中。从高速缓存中读出指令后即可解除指令。

9. 发明授权

US6134633A Prefetch management in cache memory 失效
标题翻译：缓存中的预取管理
公开(公告)号：US6134633A
公开(公告)日：2000-10-17
申请号：US961963
申请日：1997-10-31
申请人： Eino Jacobs
发明人： Eino Jacobs
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F12/0862 , G06F9/383
摘要： A computer system, a cache memory and a process, supporting prefetch operations and cache access operations so as to store information duplicated from a high level memory for use by a processing device, the processing device issuing addresses, including prefetch addresses and cache access addresses. The cache memory comprises memory resources, and prefetch resources are coupled to the memory resources and to the processing device both for receipt and storage of prefetch addresses from the processing device and for injection management of the received prefetch addresses so as to coordinate prefetch operations with cache access operations. As for the process, the invention comprises the steps of receiving prefetch addresses issued by a processing device; providing for storing, in a prefetch memory, prefetch addresses; and providing for injecting prefetch addresses in a selected order from the prefetch memory for use in fetching, into the cache memory, information associated with the prefetch addresses.
摘要翻译：一种计算机系统，高速缓冲存储器和处理，支持预取操作和高速缓存存取操作，以便存储从处理设备使用的高级存储器中复制的信息，处理设备发布地址，包括预取地址和高速缓存存取地址。高速缓存存储器包括存储器资源，并且预取资源被耦合到存储器资源和处理设备，用于从处理设备接收和存储预取地址，并且用于注入管理所接收的预取地址，以便将预取操作与高速缓存访问操作。对于该过程，本发明包括以下步骤：接收由处理设备发出的预取地址; 提供在预取存储器中存储预取地址; 并且提供从预取存储器中以选定的顺序注入预取地址，以用于将高速缓冲存储器提取与预取地址相关联的信息。

10. 发明授权

US5931939A Read crossbar elimination in a VLIW processor 失效
标题翻译：在VLIW处理器中阅读交叉开关
公开(公告)号：US5931939A
公开(公告)日：1999-08-03
申请号：US909273
申请日：1997-08-11
申请人： Eino Jacobs
发明人： Eino Jacobs
IPC分类号： G06F9/30 , G06F9/38 , H04L7/00 , G06F9/34 , G06F9/44
CPC分类号： G06F9/30141 , G06F9/30167 , G06F9/3885 , H04L7/0012
摘要： In a VLIW processor that has an instruction issue register, functional units, and a multiport register file, a portion or all of the read crossbar is eliminated.
摘要翻译：在具有指令发布寄存器，功能单元和多端口寄存器文件的VLIW处理器中，消除了读取交叉开关的一部分或全部。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式