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1. 发明申请

US20130111119A1 RAM BLOCK DESIGNED FOR EFFICIENT GANGING 有权
标题翻译： RAM块被设计用于高效率
公开(公告)号：US20130111119A1
公开(公告)日：2013-05-02
申请号：US13285210
申请日：2011-10-31
申请人： Volker Hecht , Jonathan Greene
发明人： Volker Hecht , Jonathan Greene
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , H03K19/17768 , H03K19/17796
摘要： A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.
摘要翻译：用于现场可编程门阵列的随机存取存储器块包括具有地址输入，数据输入，数据输出并且包括多个存储位置的随机存取存储器阵列。提供至少两个可编程的可逆可用输入。硬连线解码逻辑被耦合到至少两个可编程的可逆可用使能输入以选择性地启用随机存取存储器阵列。门被耦合到随机存取存储器阵列的输出，并且被配置为仅当对读操作启用随机存取存储器时才传递随机存取存储器阵列的输出，否则生成预选逻辑状态。

2. 发明授权

US08269204B2 Back to back resistive random access memory cells 有权
标题翻译：背靠背电阻随机存取存储单元
公开(公告)号：US08269204B2
公开(公告)日：2012-09-18
申请号：US12829305
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L29/02
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

3. 发明授权

US08085064B2 Logic module including versatile adder for FPGA 有权
标题翻译：逻辑模块包括FPGA通用加法器
公开(公告)号：US08085064B2
公开(公告)日：2011-12-27
申请号：US12823266
申请日：2010-06-25
申请人： Wenyi Feng , Jonathan Greene
发明人： Wenyi Feng , Jonathan Greene
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： H03K19/1737 , G06F7/503 , H03K19/17728
摘要： A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.
摘要翻译：用于FPGA的逻辑模块包括由2：1多路复用器的N级树形成的LUT。 LUT的N个输入中的每一个连接到树的一个级别中的多路复用器的选择输入。在树的叶片处的每个数据输入由产生逻辑0或逻辑1的配置存储器单元驱动。在树的最后一级的单个多路复用器的输出形成Y输出，并耦合到 XOR门的一个输入和双输入进位多路复用器的选择输入。进位多路复用器的0输入耦合到G输入。 CI输入耦合到XOR门的另一个输入端和进位复用器的1个输入端。

4. 发明授权

US07772879B1 Logic module including versatile adder for FPGA 有权
标题翻译：逻辑模块包括FPGA通用加法器
公开(公告)号：US07772879B1
公开(公告)日：2010-08-10
申请号：US12101589
申请日：2008-04-11
申请人： Wenyi Feng , Jonathan Greene
发明人： Wenyi Feng , Jonathan Greene
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/1737 , G06F7/503 , H03K19/17728
摘要： A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.
摘要翻译：用于FPGA的逻辑模块包括由2：1多路复用器的N级树形成的LUT。 LUT的N个输入中的每一个连接到树的一个级别中的多路复用器的选择输入。在树的叶片处的每个数据输入由产生逻辑0或逻辑1的配置存储器单元驱动。在树的最后一级的单个多路复用器的输出形成Y输出，并耦合到 XOR门的一个输入和双输入进位多路复用器的选择输入。进位多路复用器的0输入耦合到G输入。 CI输入耦合到XOR门的另一个输入端和进位复用器的1个输入端。

5. 发明授权

US07581117B1 Method for secure delivery of configuration data for a programmable logic device 有权
标题翻译：用于可编程逻辑器件的配置数据的安全传送的方法
公开(公告)号：US07581117B1
公开(公告)日：2009-08-25
申请号：US11185427
申请日：2005-07-19
申请人： Kenneth Irving , Jonathan Greene
发明人： Kenneth Irving , Jonathan Greene
IPC分类号： H04L9/32
CPC分类号： G06F21/14
摘要： Secure delivery of configuration data of an intellectual property (IP) core includes the steps of loading configuration data for the IP core into IP core space by an IP core provider, masking portions of the IP core space not loaded with configuration data in the loading configuration data step with the value 0 or 1 by the IP core provider, encrypting data in the IP core space by the IP core provider, loading configuration data for system design other than for the IP core into a remainder space and any unused portions of the IP core space by a system designer, masking portions of the IP core space loaded in the loading configuration data step with the value 0 or 1 used by the IP core provider in the masking portions of the IP core space not loaded step, and encrypting data in a configuration space by the system designer.
摘要翻译：知识产权（IP）核心的安全交付配置数据包括以下步骤：由IP核心提供商将IP内核的配置数据加载到IP核心空间中，掩盖在加载配置中未加载配置数据的IP核空间部分 IP核心提供商的值为0或1的数据步骤，由IP核心提供商加密IP核心空间中的数据，将用于系统设计的配置数据加载到IP核以外的剩余空间和IP的任何未使用部分通过系统设计者对IP核心空间的加载配置数据步骤中的IP核心空间的部分进行掩蔽，IP核心提供商在IP核心空间未加载步骤的掩蔽部分中使用的值为0或1的值，系统设计者的一个配置空间。

6. 发明申请

US20080007292A1 NON-VOLATILE LOOK-UP TABLE FOR AN FPGA 有权
标题翻译： FPGA的非易失性查看表
公开(公告)号：US20080007292A1
公开(公告)日：2008-01-10
申请号：US11858330
申请日：2007-09-20
申请人： John McCollum , Gregory Bakker , Jonathan Greene
发明人： John McCollum , Gregory Bakker , Jonathan Greene
IPC分类号： H03K19/177
CPC分类号： H03K19/17728
摘要： A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to Vcc through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
摘要翻译：用于FPGA的基于非易失性存储器晶体管的查找表包括n：1多路复用器。非易失性存储晶体管耦合到多路复用器的n个输入端中的每一个。如本领域已知的那样，多路复用器具有x地址输入，其中2 = n。多路复用器的输出通过上拉晶体管耦合到V cc。上拉晶体管的栅极耦合到具有耦合到多路复用器的地址输入的输入的地址转换检测器电路的输出。读出放大器耦合到多路复用器的输出端。

7. 发明授权

US09170774B2 Fast carry lookahead circuits 有权
标题翻译：快速携带查找电路
公开(公告)号：US09170774B2
公开(公告)日：2015-10-27
申请号：US13494850
申请日：2012-06-12
申请人： Volker Hecht , Marcel Derevlean , Jonathan Greene
发明人： Volker Hecht , Marcel Derevlean , Jonathan Greene
IPC分类号： G06F7/508
CPC分类号： G06F7/508
摘要： A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
摘要翻译：快速前瞻进位加法器包括耦合到加法器逻辑的加法器逻辑和先行进位逻辑逻辑。进位路径逻辑具有主进位路径，进位入口路径和进位出口路径，进位路径与进位出口路径分离。

8. 发明授权

US08868820B2 RAM block designed for efficient ganging 有权
标题翻译： RAM块设计用于高效组合
公开(公告)号：US08868820B2
公开(公告)日：2014-10-21
申请号：US13285210
申请日：2011-10-31
申请人： Volker Hecht , Jonathan Greene
发明人： Volker Hecht , Jonathan Greene
IPC分类号： G06F12/00 , H03K19/177
CPC分类号： G06F12/00 , H03K19/17768 , H03K19/17796
摘要： A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.
摘要翻译：用于现场可编程门阵列的随机存取存储器块包括具有地址输入，数据输入，数据输出并且包括多个存储位置的随机存取存储器阵列。提供至少两个可编程的可逆可用输入。硬连线解码逻辑被耦合到至少两个可编程的可逆可用使能输入以选择性地启用随机存取存储器阵列。门被耦合到随机存取存储器阵列的输出，并且被配置为仅当对读操作启用随机存取存储器时才传递随机存取存储器阵列的输出，否则生成预选逻辑状态。

9. 发明授权

US08446170B2 FPGA RAM blocks optimized for use as register files 有权
标题翻译：优化的FPGA RAM块用作寄存器文件
公开(公告)号：US08446170B2
公开(公告)日：2013-05-21
申请号：US13463232
申请日：2012-05-03
申请人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
发明人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , G11C8/16 , H03K19/1776
摘要： A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
摘要翻译：公开了一种适用于现场可编程门阵列集成电路器件的随机存取存储器电路。 FPGA具有可编程阵列，其具有逻辑模块和路由互连，可编程地耦合到逻辑模块和RAM电路。 RAM电路具有三个端口：第一可读端口，第二可读端口和可写入端口。读端口可以是可编程同步的或异步的，并且具有可编程可旁路输出流水线寄存器。 RAM电路特别适用于实现寄存器文件。还描述了一种新颖的互连方法。

10. 发明申请

US20120259908A1 FAST CARRY LOOKAHEAD CIRCUITS 有权
标题翻译：快速携带LOOKAHEAD电路
公开(公告)号：US20120259908A1
公开(公告)日：2012-10-11
申请号：US13494850
申请日：2012-06-12
申请人： Volker Hecht , Marcel Derevlean , Jonathan Greene
发明人： Volker Hecht , Marcel Derevlean , Jonathan Greene
IPC分类号： G06F7/508
CPC分类号： G06F7/508
摘要： A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
摘要翻译：快速前瞻进位加法器包括耦合到加法器逻辑的加法器逻辑和先行进位逻辑逻辑。进位路径逻辑具有主进位路径，进位入口路径和进位出口路径，进位路径与进位出口路径分离。

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