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1. 发明申请

US20110001115A1 RESISTIVE RAM DEVICES FOR PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：用于可编程逻辑器件的电阻RAM器件
公开(公告)号：US20110001115A1
公开(公告)日：2011-01-06
申请号：US12829300
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L45/00
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

2. 发明申请

US20110001116A1 BACK TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS 有权
标题翻译：返回电阻随机存取存储器
公开(公告)号：US20110001116A1
公开(公告)日：2011-01-06
申请号：US12829305
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L45/00
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

3. 发明授权

US08269203B2 Resistive RAM devices for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的电阻式RAM器件
公开(公告)号：US08269203B2
公开(公告)日：2012-09-18
申请号：US12829300
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L29/02
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

4. 发明申请

US20130221316A1 FRONT TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS 有权
标题翻译：前端电阻随机存取存储器
公开(公告)号：US20130221316A1
公开(公告)日：2013-08-29
申请号：US13840815
申请日：2013-03-15
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L45/00
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上方形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

5. 发明授权

US08415650B2 Front to back resistive random access memory cells 有权
标题翻译：从前到后的电阻随机存取存储单元
公开(公告)号：US08415650B2
公开(公告)日：2013-04-09
申请号：US12829311
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L29/02
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory cell is formed on a semiconductor substrate. First and second diffused regions are disposed in the semiconductor substrate. A polysilicon gate is disposed above the first and second diffused regions. A first contact connects the first diffused region with a region of a first metal layer. A first interlayer dielectric layer is formed over the first metal layer and includes first and second vias, each including conductive plugs connected to the region of the first metal layer. First and second resistive random access memory devices formed over the first interlayer dielectric layer have first and second terminals, and include a dielectric layer and an ion source layer. The first terminals of the first and second resistive random access memory devices are coupled to the first metal layer by the first and second conductive plugs.
摘要翻译：电阻性随机存取存储单元形成在半导体衬底上。第一和第二扩散区域设置在半导体衬底中。多晶硅栅极设置在第一和第二扩散区域上方。第一接触将第一扩散区域与第一金属层的区域连接。第一层间电介质层形成在第一金属层之上，并且包括第一和第二通孔，每个通孔包括连接到第一金属层的区域的导电插塞。形成在第一层间介质层上的第一和第二电阻随机存取存储器件具有第一和第二端子，并且包括电介质层和离子源层。第一和第二电阻随机存取存储器件的第一端子通过第一和第二导电插塞耦合到第一金属层。

6. 发明申请

US20110001108A1 FRONT TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS 有权
标题翻译：前端电阻随机存取存储器
公开(公告)号：US20110001108A1
公开(公告)日：2011-01-06
申请号：US12829311
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L45/00
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

7. 发明授权

US08269204B2 Back to back resistive random access memory cells 有权
标题翻译：背靠背电阻随机存取存储单元
公开(公告)号：US08269204B2
公开(公告)日：2012-09-18
申请号：US12829305
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L29/02
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

8. 发明申请

US20080197450A1 AMORPHOUS CARBON METAL-TO-METAL ANTIFUSE WITH ADHESION PROMOTING LAYERS 审中-公开
标题翻译：非粘性金属对金属抗粘附剂与粘合促进层
公开(公告)号：US20080197450A1
公开(公告)日：2008-08-21
申请号：US12103550
申请日：2008-04-15
申请人： Frank W. Hawley , A. Farid Issaq , John L. McCollum , Shubhra M. Gangopadhyay , Jorge A. Lubguban , Jin Miao Shen
发明人： Frank W. Hawley , A. Farid Issaq , John L. McCollum , Shubhra M. Gangopadhyay , Jorge A. Lubguban , Jin Miao Shen
IPC分类号： H01L23/525
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S257/903 , H01L2924/00
摘要： A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1±0.4, and the ratio of x to y in SixNy is in a range of about 0.75±0.225.
摘要翻译：具有下金属电极的金属对金属反熔丝，设置在下金属电极上的下薄增粘层，设置在薄粘附促进层上的无定形碳反应熔剂层，设置在所述反熔丝之上的上薄增粘层材料层和上部金属电极。薄粘附促进层的厚度约为2埃至20埃，并且来自选自包含Si x Si x Si和Si x的组的材料， / SUB> Y 。 Si x Si x y中的x与y的比率在约1±0.4的范围内，并且Si x x y中的x与y的比例， SUB> N 在约0.75±0.225的范围内。

9. 发明授权

US5741720A Method of programming an improved metal-to-metal via-type antifuse 失效
标题翻译：编制改进的金属对金属通孔型反熔丝的方法
公开(公告)号：US5741720A
公开(公告)日：1998-04-21
申请号：US538962
申请日：1995-10-04
申请人： Frank W. Hawley , Abdelshafy A. Eltoukhy , John L. McCollum
发明人： Frank W. Hawley , Abdelshafy A. Eltoukhy , John L. McCollum
IPC分类号： H01L20060101 , H01L21/70 , H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： A metal-to-metal antifuse disposed between two aluminum metallization layers in a CMOS integrated circuit or similar structure includes an antifuse material layer having an aluminum-free conductive link. The aluminum-free link is formed by forming a first barrier metal layer out of TiN having a first thickness, a second barrier metal layer out of TiN having a second thickness which may be less than said first thickness, the first and second barrier metal layers separating the antifuse material layer from first and second electrodes. The antifuse is programmed by applying a voltage potential capable of programming the antifuse across the electrodes with the more positive side of the potential applied to the electrode adjacent the barrier metal layer having the least thickness. In another aspect of the invention, an antifuse having a first barrier metal layer of a first thickness and a second barrier metal layer of a second thickness may be fabricated wherein the first thickness is less than the second thickness and wherein programming of the antifuse is accomplished by placing the more positive voltage of the programming voltage supply on the electrode of the antifuse adjacent the first barrier metal layer.
摘要翻译：设置在CMOS集成电路或类似结构中的两个铝金属化层之间的金属对金属反熔丝包括具有无铝导电连接的反熔丝材料层。通过从具有第一厚度的TiN形成第一阻挡金属层，形成具有第二厚度的第二阻挡金属层，形成第一阻挡金属层，第二厚度可以小于所述第一厚度，第一和第二阻挡金属层将反熔丝材料层与第一和第二电极分离。通过施加能够跨越电极编程反熔丝的电压电位来编程反熔丝，其中施加到邻近具有最小厚度的阻挡金属层的电极的电势的更正的一侧。在本发明的另一方面，可以制造具有第一厚度的第一阻挡金属层和第二厚度的第二阻挡金属层的反熔丝，其中第一厚度小于第二厚度，并且其中完成反熔丝的编程通过将编程电压源的正电压放置在与第一阻挡金属层相邻的反熔丝的电极上。

10. 发明授权

US5308795A Above via metal-to-metal antifuse 失效
标题翻译：以上通过金属对金属反熔丝
公开(公告)号：US5308795A
公开(公告)日：1994-05-03
申请号：US971734
申请日：1992-11-04
申请人： Frank W. Hawley , Yen Yeouchung
发明人： Frank W. Hawley , Yen Yeouchung
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5252 , H01L2924/0002 , Y10S148/055
摘要： A method for fabricating a metal-to-metal antifuse comprises the steps of (1) forming and defining a first metal interconnect layer; (2) forming an interlayer dielectric layer; (3) forming an antifuse via in the interlayer dielectric layer to expose the first metal interconnect layer; (4) depositing a via metal layer into a portion of the volume defining the antifuse via; (5) forming a planarizing layer of an insulating material in the antifuse via sufficient to fill a remaining portion of the volume defining the antifuse via; (6) etching the planarizing layer to expose an upper surface of the via metal layer and an upper surface of the interlayer dielectric layer so as to form a substantially planar surface comprising the upper surface of the interlayer dielectric layer, the planarizing layer, and the upper surface of the via metal layer; (7) forming an antifuse material layer over the substantially planar surface; (8) forming a metal capping layer over the antifuse material layer; and (9) defining the antifuse material layer and the metal capping layer.
摘要翻译：制造金属对金属反熔丝的方法包括以下步骤：（1）形成和限定第一金属互连层; （2）形成层间电介质层; （3）在所述层间电介质层中形成反熔丝通孔以暴露所述第一金属互连层; （4）将通孔金属层沉积到限定反熔丝通孔的体积的一部分中; （5）在所述反熔丝中形成绝缘材料的平坦化层，以足以填充限定所述反熔丝通孔的所述体积的剩余部分; （6）蚀刻平坦化层以暴露通孔金属层的上表面和层间电介质层的上表面，以便形成基本平坦的表面，该表面包括层间电介质层的上表面，平坦化层和通孔金属层的上表面; （7）在所述基本上平坦的表面上形成反熔丝材料层; （8）在所述反熔丝材料层上形成金属覆盖层; 和（9）限定反熔丝材料层和金属覆盖层。

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