专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07351362B2 Photochromic material 有权
标题翻译：光致变色材料
公开(公告)号：US07351362B2
公开(公告)日：2008-04-01
申请号：US10892156
申请日：2004-07-16
申请人： Michiyuki Yasuda , Jun Sugai , Fumihiro Kimura
发明人： Michiyuki Yasuda , Jun Sugai , Fumihiro Kimura
IPC分类号： G02B5/23 , C09K9/02 , C08K5/35 , G03C1/66
CPC分类号： C08K5/357 , Y10S428/913
摘要： A photochromic material comprising a styrene-based oligomer having a weight average molecular weight of from 200 to 6000 and a photochromic compound selected from the group consisting of spirooxazine derivatives and spiropyran derivatives.
摘要翻译：包含重均分子量为200-6000的苯乙烯基低聚物和选自螺恶嗪衍生物和螺吡喃衍生物的光致变色化合物的光致变色材料。

2. 发明授权

US07269807B2 Area ratio/occupancy ratio verification method and pattern generation method 有权
标题翻译：面积比/占有率验证方法和图案生成方法
公开(公告)号：US07269807B2
公开(公告)日：2007-09-11
申请号：US10886704
申请日：2004-07-09
申请人： Junichi Shimada , Fumihiro Kimura , Mitsumi Ito , Kiyohito Mukai
发明人： Junichi Shimada , Fumihiro Kimura , Mitsumi Ito , Kiyohito Mukai
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Verification of the pattern area ratio of a semiconductor integrated circuit device or the pattern occupancy ratio in a check window set for the semiconductor integrated circuit device is performed on an assumption that a dummy pattern defined by process conditions is placed in an unoccupied region of the semiconductor integrated circuit device or in an unoccupied region in at least one instance provided in the semiconductor integrated circuit device.
摘要翻译：在半导体集成电路器件设定的检查窗口中，对半导体集成电路器件的图案面积比率或图案占有率的验证是在将由工艺条件限定的虚设图案置于半导体集成电路的未占用区域中的假设下进行的集成电路器件或在半导体集成电路器件中提供的至少一个实例中的未占用区域中。

3. 发明申请

US20060101367A1 Design method of semiconductor device and semiconductor device 审中-公开
标题翻译：半导体器件和半导体器件的设计方法
公开(公告)号：US20060101367A1
公开(公告)日：2006-05-11
申请号：US11262966
申请日：2005-11-01
申请人： Kazuhisa Fujita , Fumihiro Kimura , Takayuki Araki
发明人： Kazuhisa Fujita , Fumihiro Kimura , Takayuki Araki
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5081
摘要： In an error analysis step, analysis of an antenna effect error, a timing constraint violation and the like is performed for layout data in which redundant via conversion has been performed. Then, whether or not an error exists is judged and, among redundant vias located on a signal line in which a design constraint violation has occurred, how many vias have to be converted to single vias, respectively, to avoid the design constraint violation is calculated. In a via conversion step, a redundant via which has caused an error is converted to a single via, based on a result of the calculation. Thus, a design constraint violation regarding an error such as an antenna effect error and a timing constraint violation caused by a redundant via obtained by converting a single via for improving yield hardly occurs.
摘要翻译：在误差分析步骤中，对已执行冗余通过转换的布局数据执行天线效应误差，定时约束违规等的分析。然后，判断是否存在错误，并且在发生设计约束违规的信号线上的冗余通孔中，分别需要将多少个通孔转换为单个过孔以避免设计约束违规。在通孔转换步骤中，基于计算结果将导致错误的冗余通道转换为单个通孔。因此，几乎不发生关于由通过转换单个通路而获得的冗余通路引起的诸如天线效应误差和定时约束违规之类的错误的设计约束违规。

4. 发明授权

US06708318B2 Wiring resistance correcting method 有权
标题翻译：接线电阻校正方法
公开(公告)号：US06708318B2
公开(公告)日：2004-03-16
申请号：US09963563
申请日：2001-09-27
申请人： Kazuhiro Satoh , Fumihiro Kimura
发明人： Kazuhiro Satoh , Fumihiro Kimura
IPC分类号： G06F1750
CPC分类号： G06F17/5077 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Where there are wirings with different film thicknesses or a sheet resistance in a non-scraped state of a wiring layer cannot be obtained as a result of the CPM technique, a wiring resistance according to a film thickness when an LSI is manufactured is acquired by automatic processing to reduce its difference from a real resistance, and accurate voltage drop analysis is carried out to reduce malfunction in a real chip. In a semiconductor circuit device with a plurality of kinds of film thicknesses in the same wiring layer, with a variation occurring in the wiring film thickness when wirings are formed on a silicon wafer, or a warp occurring in an upper layer because the stacking of lower layers is not uniform in the manufacturing process of the wiring, an error of the wiring resistance due to the difference in the film thickness or warp of the wiring is corrected to produce a virtual layout data.
摘要翻译：在采用CPM技术的情况下，由于不能获得具有不同膜厚度的布线或布线层的无刮擦状态的薄层电阻，因此通过自动获取当制造LSI时根据膜厚度的布线电阻处理以减少与实际电阻的差异，并进行精确的电压降分析以减少真实芯片中的故障。在同一布线层中具有多种膜厚的半导体电路器件中，当在硅晶片上形成布线时发生在布线膜厚度上的变化，或由于下层叠层而产生的翘曲在布线的制造过程中层数不均匀，校正了由于膜厚度的差异或布线翘曲引起的布线电阻的误差，从而产生虚拟布局数据。

5. 发明申请

US20090020784A1 METHOD FOR DESIGNING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于设计半导体器件和半导体器件的方法
公开(公告)号：US20090020784A1
公开(公告)日：2009-01-22
申请号：US12236949
申请日：2008-09-24
申请人： Takayuki Araki , Fumihiro Kimura , Junichi Shimada , Kazuhisa Fujita
发明人： Takayuki Araki , Fumihiro Kimura , Junichi Shimada , Kazuhisa Fujita
IPC分类号： H01L29/76
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A method for designing a semiconductor device and a semiconductor device of the present invention permits the achievement of a predetermined pattern area ratio while power supply lines are reinforced by connecting a dummy metal line, which is formed in an unoccupied region of a wiring layer for the purpose of achieving the predetermined area ratio, at its two or more points with a power supply line for VDD or VSS.
摘要翻译：本发明的半导体器件和半导体器件的设计方法可以通过连接形成在布线层的未占用区域中的虚设金属线来增强电源线，从而实现预定的图案面积比，在其两个或更多点用VDD或VSS的电源线实现预定面积比的目的。

6. 发明申请

US20050172248A1 Area ratio/occupancy ratio verification method and pattern generation method 有权
标题翻译：面积比/占有率验证方法和图案生成方法
公开(公告)号：US20050172248A1
公开(公告)日：2005-08-04
申请号：US10886704
申请日：2004-07-09
申请人： Junichi Shimada , Fumihiro Kimura , Mitsumi Ito , Kiyohito Mukai
发明人： Junichi Shimada , Fumihiro Kimura , Mitsumi Ito , Kiyohito Mukai
IPC分类号： G06F17/50 , G06F9/45 , H01L21/3205 , H01L21/82 , H01L23/52
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Verification of the pattern area ratio of a semiconductor integrated circuit device or the pattern occupancy ratio in a check window set for the semiconductor integrated circuit device is performed on an assumption that a dummy pattern defined by process conditions is placed in an unoccupied region of the semiconductor integrated circuit device or in an unoccupied region in at least one instance provided in the semiconductor integrated circuit device.
摘要翻译：假设半导体集成电路器件的模式面积比的验证或半导体集成电路器件设置的检查窗口中的图案占有率是在将半导体集成电路器件的未占用区域放置在由半导体集成电路器件的未占用区域集成电路器件或在半导体集成电路器件中设置的至少一个实例中的未占用区域中。

7. 发明授权

US08028264B2 Semiconductor device and semiconductor device layout designing method 有权
标题翻译：半导体器件和半导体器件布局设计方法
公开(公告)号：US08028264B2
公开(公告)日：2011-09-27
申请号：US11790736
申请日：2007-04-27
申请人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
发明人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
IPC分类号： G06F17/50
CPC分类号： H01L27/0203 , H01L27/118
摘要： A semiconductor device including a plurality of cells having an antenna protection element and a cell other than the antenna protection element; and a first dummy pattern and a second dummy pattern arranged in a layer above the plurality of cells. Further, the first dummy pattern overlaps with the antenna protection element, the second dummy pattern overlaps with the cell other than the antenna protection element, and a first layout rule of the first dummy pattern is different from a second layout rule of the second dummy pattern.
摘要翻译：一种半导体器件，包括具有天线保护元件和除天线保护元件之外的单元的多个单元; 以及布置在所述多个单元上方的层中的第一虚设图案和第二虚设图案。此外，第一伪图案与天线保护元件重叠，第二虚设图案与天线保护元件以外的单元重叠，并且第一虚设图案的第一布局规则与第二虚设图案的第二布局规则不同。

8. 发明授权

US07913221B2 Interconnect structure of semiconductor integrated circuit, and design method and device therefor 有权
标题翻译：半导体集成电路的互连结构及其设计方法及装置
公开(公告)号：US07913221B2
公开(公告)日：2011-03-22
申请号：US11907999
申请日：2007-10-19
申请人： Hirofumi Miyashita , Chie Kabuo , Nobuyuki Iwauchi , Yoichi Matsumura , Fumihiro Kimura , Tatsuo Gou , Yukiji Hashimoto
发明人： Hirofumi Miyashita , Chie Kabuo , Nobuyuki Iwauchi , Yoichi Matsumura , Fumihiro Kimura , Tatsuo Gou , Yukiji Hashimoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5077 , H01L21/7682
摘要： A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).
摘要翻译：一种在半导体集成电路器件中设计互连层的互连结构的方法，包括以下步骤：（a）输入半导体集成电路器件的布局数据; （b）控制布局数据中的基于气隙排除区域的互连; 和（c）输出包括在步骤（b）中确定的气隙排除区的布局数据。

9. 发明授权

US06818929B2 Standard cell for plural power supplies and related technologies 失效
标题翻译：标准电池用于多种电源及相关技术
公开(公告)号：US06818929B2
公开(公告)日：2004-11-16
申请号：US10455387
申请日：2003-06-06
申请人： Masanori Tsutsumi , Junichi Yano , Fumihiro Kimura , Masayuki Matsuda
发明人： Masanori Tsutsumi , Junichi Yano , Fumihiro Kimura , Masayuki Matsuda
IPC分类号： H01L2710
CPC分类号： H01L27/11807
摘要： A standard cell for a plurality of power supplies comprises a first power line and a second power line electrically isolated from the first power line. An N well is arranged in spaced relation with the whole peripheral boundaries of the standard cell. In the case where the standard cells are arranged adjacently to each other in the direction along the power lines or in the direction orthogonal thereto, the N well in the standard cell for a plurality of power supplies is isolated from the N wells of the adjacent standard cells in the direction along the power lines or in the direction orthogonal thereto, as the case may be.
摘要翻译：用于多个电源的标准单元包括与第一电力线电隔离的第一电力线和第二电力线。 N阱与标准单元的整个外围边界间隔开排列。在标准单元沿着电力线的方向或与其正交的方向相邻布置的情况下，用于多个电源的标准单元中的N阱与相邻标准的N个阱隔离视情况而定，沿着电力线或与其正交的方向的电池。

10. 发明授权

US5978572A LSI wire length estimation and area estimation 失效
标题翻译： LSI线长度估计和面积估计
公开(公告)号：US5978572A
公开(公告)日：1999-11-02
申请号：US915723
申请日：1997-08-21
申请人： Masahiko Toyonaga , Fumihiro Kimura , Minako Fukumoto , Noriko Koshita
发明人： Masahiko Toyonaga , Fumihiro Kimura , Minako Fukumoto , Noriko Koshita
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The wire length of an LSI is estimated from a netlist describing connection information of the LSI and a cell library storing information as to cells used in the LSI design, with performing no rough placement and rough wiring by a layout system. Information necessary for wire length estimation is extracted from the netlist and the cell library. A net basic wire length is determined for each fan-out. In a net wire length estimating step, a net wire length for each fan-out is estimated by making reference to the determined net basic wire length and taking into account net expansion due to the cell distribution in a cell placement. Additionally, taking into account a terminal distribution and the aspect ratio of an estimation-target block, a correction on the estimated net wire length is made. From the corrected net wire length, the total wire length of the estimation-target block is estimated.
摘要翻译：从描述LSI的连接信息的网表和存储关于LSI设计中使用的单元的信息的单元库来估计LSI的线长度，不进行布局系统的粗糙布置和粗糙布线。从网表和单元库中提取线长估计所需的信息。确定每个扇出的净基本线长度。在网线长度估计步骤中，通过参考确定的净基线长度并考虑由于单元布置中的单元分布引起的净扩展来估计每个扇出的净线长度。此外，考虑到估计目标块的终端分布和纵横比，对估计的网线长度进行校正。根据校正的网线长度，估计估计对象块的总线长度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式