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1. 发明授权

US08552550B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08552550B2
公开(公告)日：2013-10-08
申请号：US13397826
申请日：2012-02-16
申请人： Junichi Shimada , Hidenori Shibata , Tsutomu Fujii , Hiromasa Fukazawa , Nobuyuki Iwauchi , Takeya Fujino
发明人： Junichi Shimada , Hidenori Shibata , Tsutomu Fujii , Hiromasa Fukazawa , Nobuyuki Iwauchi , Takeya Fujino
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/522 , H01L21/76819 , H01L21/7684 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor device having a multilayer wiring structure, in which a dummy pattern is formed in a wiring void with favorable manufacturing efficiency. In a semiconductor device having a multilayer wiring structure, dummy pattern (21) is formed in relatively narrow wiring void (Area_S1) so as to extend in a direction different from that of dummy patterns (22, 23) formed in relatively wide wiring void (Area_S2).
摘要翻译：公开了一种具有多层布线结构的半导体器件，其中虚拟图案形成在布线空隙中并具有良好的制造效率。在具有多层布线结构的半导体器件中，在比较窄的布线空隙（Area_S1）中形成虚拟图案（21），以沿与形成在相对宽的布线空隙中的虚拟图案（22,23）不同的方向延伸 Area_S2）。

2. 发明申请

US20090193374A1 METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, DESIGNING APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：设计半导体集成电路器件，设计器件和半导体集成电路器件的方法
公开(公告)号：US20090193374A1
公开(公告)日：2009-07-30
申请号：US12352206
申请日：2009-01-12
申请人： Kazuhiko FUJIMOTO , Kenji Yokoyama , Takeya Fujino , Takako Ohashi , Hiromasa Fukazawa , Yohei Takagi , Kazuhisa Fujita
发明人： Kazuhiko FUJIMOTO , Kenji Yokoyama , Takeya Fujino , Takako Ohashi , Hiromasa Fukazawa , Yohei Takagi , Kazuhisa Fujita
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F17/5031 , H01L24/02 , H01L2924/01004 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： As a method for considering the adverse influence of the stresses caused form the pad, two sorts of methods are provided. As one method, while delay variation values of cells caused by an adverse influence of stresses are calculated, the calculated delay variation values are applied to the cells so as to perform a timing analysis, and the like by considering the adverse influence of the stresses. Then, in order that a flip chip type LSI is designed by employing a result of the above-described analysis in such a manner that the adverse influence of the stresses applied from the pad is not given to vias, wiring lines, and cells located under the pad, such a physical structure that no via is arranged under the pad is employed.
摘要翻译：作为考虑由衬垫引起的应力的不利影响的方法，提供了两种方法。作为一种方法，当计算由应力的不利影响引起的电池的延迟变化值时，将所计算的延迟变化值应用于电池，以便通过考虑应力的不利影响进行定时分析等。然后，为了通过采用上述分析的结果来设计倒装芯片型LSI，使得不会对由焊盘施加的应力的不利影响赋予位于下面的通孔，布线和电池采用垫，这样的物理结构，没有通孔布置在垫下方。

3. 发明授权

US08028264B2 Semiconductor device and semiconductor device layout designing method 有权
标题翻译：半导体器件和半导体器件布局设计方法
公开(公告)号：US08028264B2
公开(公告)日：2011-09-27
申请号：US11790736
申请日：2007-04-27
申请人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
发明人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
IPC分类号： G06F17/50
CPC分类号： H01L27/0203 , H01L27/118
摘要： A semiconductor device including a plurality of cells having an antenna protection element and a cell other than the antenna protection element; and a first dummy pattern and a second dummy pattern arranged in a layer above the plurality of cells. Further, the first dummy pattern overlaps with the antenna protection element, the second dummy pattern overlaps with the cell other than the antenna protection element, and a first layout rule of the first dummy pattern is different from a second layout rule of the second dummy pattern.
摘要翻译：一种半导体器件，包括具有天线保护元件和除天线保护元件之外的单元的多个单元; 以及布置在所述多个单元上方的层中的第一虚设图案和第二虚设图案。此外，第一伪图案与天线保护元件重叠，第二虚设图案与天线保护元件以外的单元重叠，并且第一虚设图案的第一布局规则与第二虚设图案的第二布局规则不同。

4. 发明申请

US20120139101A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120139101A1
公开(公告)日：2012-06-07
申请号：US13397826
申请日：2012-02-16
申请人： JUNICHI SHIMADA , HIDENORI SHIBATA , TSUTOMU FUJII , HIROMASA FUKAZAWA , NOBUYUKI IWAUCHI , TAKEYA FUJINO
发明人： JUNICHI SHIMADA , HIDENORI SHIBATA , TSUTOMU FUJII , HIROMASA FUKAZAWA , NOBUYUKI IWAUCHI , TAKEYA FUJINO
IPC分类号： H01L23/49
CPC分类号： H01L23/522 , H01L21/76819 , H01L21/7684 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor device having a multilayer wiring structure, in which a dummy pattern is formed in a wiring void with favorable manufacturing efficiency. In a semiconductor device having a multilayer wiring structure, dummy pattern (21) is formed in relatively narrow wiring void (Area_S1) so as to extend in a direction different from that of dummy patterns (22, 23) formed in relatively wide wiring void (Area_S2).
摘要翻译：公开了一种具有多层布线结构的半导体器件，其中虚拟图案形成在布线空隙中并具有良好的制造效率。在具有多层布线结构的半导体器件中，在比较窄的布线空隙（Area_S1）中形成虚拟图案（21），以沿与形成在相对宽的布线空隙中的虚拟图案（22,23）不同的方向延伸 Area_S2）。

5. 发明授权

US06989597B2 Semiconductor integrated circuit and method of manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06989597B2
公开(公告)日：2006-01-24
申请号：US10685387
申请日：2003-10-16
申请人： Takeya Fujino , Fumihiro Kimura
发明人： Takeya Fujino , Fumihiro Kimura
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Prevention of coming off of the layer where the contacts are formed and the isolating film and breakage of the LSI is realized. To do this, a contact array is provided in which a plurality of contacts is formed so as to be aligned in the vertical and the horizontal directions. In the contact array, the contact formation spacing in both of the vertical and the horizontal directions is larger than the contact formation spacing determined by the manufacturing process. Consequently, the number of contacts formed in the contact array can be reduced to not more than the number of contacts that can be formed in the unit area determined by the process, so that prevention of coming off of the layer where the contacts are formed and the isolating film and breakage of the LSI can be realized.
摘要翻译：防止形成触点的层的脱落和LSI的隔离膜破损。为此，提供一种接触阵列，其中多个触点形成为在垂直和水平方向上对齐。在接触阵列中，垂直和水平方向上的接触形成间距大于由制造过程确定的接触形成间距。因此，可以将形成在接触阵列中的触点的数量减少到不大于在由该工艺确定的单位面积中形成的触点的数量，从而防止形成触点的层的脱落;以及可以实现LSI的隔离膜和断裂。

6. 发明申请

US20070252258A1 Semiconductor device and semiconductor device layout designing method 有权
标题翻译：半导体器件和半导体器件布局设计方法
公开(公告)号：US20070252258A1
公开(公告)日：2007-11-01
申请号：US11790736
申请日：2007-04-27
申请人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
发明人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
IPC分类号： H01L23/02 , G08B13/14 , H01Q9/04
CPC分类号： H01L27/0203 , H01L27/118
摘要： In each wiring layer in which wirings connected to a gate is formed, wirings are routed so as not to cover the active region of an antenna protection element. A wiring formed in an upper wiring layer is routed so as to cover at least a part of the active region of the antenna protection element.
摘要翻译：在形成连接到栅极的布线的每个布线层中，布线被布线成不覆盖天线保护元件的有源区。形成在上布线层中的布线被布线以覆盖天线保护元件的有源区域的至少一部分。

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