专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08400854B2 Identifying at-risk data in non-volatile storage 有权
标题翻译：识别非易失性存储中的风险数据
公开(公告)号：US08400854B2
公开(公告)日：2013-03-19
申请号：US12694118
申请日：2010-01-26
申请人： Gen Pei , Lanlan Gu , Nima Mokhlesi , Idan Alrod , Eran Sharon , Itshak Afriat
发明人： Gen Pei , Lanlan Gu , Nima Mokhlesi , Idan Alrod , Eran Sharon , Itshak Afriat
IPC分类号： G11C29/04 , G11C29/06
CPC分类号： G11C16/3418 , G06F11/1072
摘要： The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use.
摘要翻译：非易失性存储系统基于性能数据预测哪些块（或其他存储单元）将变坏。预测为坏的那些块中的用户数据可以被重新编程到其他块，并且预测为坏的块可以被进一步使用。

2. 发明授权

US07943999B2 Stress enhanced MOS circuits 有权
标题翻译：应力增强MOS电路
公开(公告)号：US07943999B2
公开(公告)日：2011-05-17
申请号：US12208196
申请日：2008-09-10
申请人： Gen Pei
发明人： Gen Pei
IPC分类号： H01L27/08
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/823807 , H01L21/84 , H01L29/4925 , H01L29/66772 , H01L29/7845 , H01L29/78654
摘要： A stress enhanced MOS circuit is provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness overlying the layer of polycrystalline silicon. A stress liner overlies the side walls of the gate electrode.
摘要翻译：提供了一种应力增强型MOS电路。应力增强型MOS电路包括半导体衬底和覆盖半导体衬底的栅极绝缘体。栅电极覆盖栅极绝缘体; 栅电极具有侧壁并且包括具有与栅极绝缘体接触的第一厚度的多晶硅层和具有大于覆盖多晶硅层的第一厚度的第二厚度的导电应力材料层。应力衬垫覆盖在栅电极的侧壁上。

3. 发明申请

US20090242989A1 COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE WITH EMBEDDED STRESSOR 审中-公开
标题翻译：具有嵌入式压力的补充金属氧化物半导体器件
公开(公告)号：US20090242989A1
公开(公告)日：2009-10-01
申请号：US12054933
申请日：2008-03-25
申请人： KEVIN K. CHAN , Jack O. Chu , Jin-Ping Han , Thomas S. Kanarsky , Hung Y. Ng , Qiqing Quyang , Gen Pei , Chun-Yung Sung , Henry K. Utomo , Thomas A. Wallner
发明人： KEVIN K. CHAN , Jack O. Chu , Jin-Ping Han , Thomas S. Kanarsky , Hung Y. Ng , Qiqing Quyang , Gen Pei , Chun-Yung Sung , Henry K. Utomo , Thomas A. Wallner
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78687 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66742 , H01L29/7848 , H01L29/78621
摘要： In one embodiment, the invention is a complementary metal-oxide-semiconductor device with an embedded stressor. One embodiment of a field effect transistor includes a silicon on insulator channel, a gate electrode coupled to the silicon on insulator channel, and a stressor embedded in the silicon on insulator channel and spaced laterally from the gate electrode, where the stressor is formed of a silicon germanide alloy whose germanium content gradually increases in one direction.
摘要翻译：在一个实施例中，本发明是具有嵌入式应力源的互补金属氧化物半导体器件。场效应晶体管的一个实施例包括硅绝缘体沟道，耦合到绝缘体上硅沟道上的栅电极和嵌入在绝缘体上硅沟道中并与栅电极横向隔开的应力源，其中应力源由锗锗合金的锗含量在一个方向逐渐增加。

4. 发明申请

US20090146212A1 NEGATIVE DIFFERENTIAL RESISTANCE DIODE AND SRAM UTILIZING SUCH DEVICE 有权
标题翻译：负极差电阻二极管和使用此类器件的SRAM
公开(公告)号：US20090146212A1
公开(公告)日：2009-06-11
申请号：US12368775
申请日：2009-02-10
申请人： Gen Pei , Zoran Krivokapic
发明人： Gen Pei , Zoran Krivokapic
IPC分类号： H01L27/06
CPC分类号： H01L27/11 , H01L29/7391
摘要： A negative differential resistance (NDR) diode and a memory cell incorporating that NDR diode are provided. The NDR diode comprises a p-type germanium region in contact with an n-type germanium region and forming a germanium pn junction diode. A first gate electrode overlies the p-type germanium region, is electrically coupled to the n-type germanium region, and is configured for coupling to a first electrical potential. A second gate electrode overlies the n-type germanium region and is configured for coupling to a second electrical potential. A third electrode is electrically coupled to the p-type germanium region and may be coupled to the second gate electrode. A small SRAM cell uses two such NDR diodes with a single pass transistor.
摘要翻译：提供负差分电阻（NDR）二极管和包含该NDR二极管的存储单元。 NDR二极管包括与n型锗区接触并形成锗pn结二极管的p型锗区。第一栅电极覆盖在p型锗区上，电耦合到n型锗区，并且被配置为耦合到第一电位。第二栅电极覆盖在n型锗区上，并被配置成耦合到第二电位。第三电极电耦合到p型锗区域并且可以耦合到第二栅电极。一个小的SRAM单元使用两个这样的NDR二极管与单通道晶体管。

5. 发明授权

US07439120B2 Method for fabricating stress enhanced MOS circuits 有权
标题翻译：制造应力增强型MOS电路的方法
公开(公告)号：US07439120B2
公开(公告)日：2008-10-21
申请号：US11464090
申请日：2006-08-11
申请人： Gen Pei
发明人： Gen Pei
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/823807 , H01L21/84 , H01L29/4925 , H01L29/66772 , H01L29/7845 , H01L29/78654
摘要： A stress enhanced MOS circuit and methods for its fabrication are provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness overlying the layer of polycrystalline silicon. A stress liner overlies the side walls of the gate electrode.
摘要翻译：提供一种应力增强型MOS电路及其制造方法。应力增强型MOS电路包括半导体衬底和覆盖半导体衬底的栅极绝缘体。栅电极覆盖栅极绝缘体; 栅电极具有侧壁并且包括具有与栅极绝缘体接触的第一厚度的多晶硅层和具有大于覆盖多晶硅层的第一厚度的第二厚度的导电应力材料层。应力衬垫覆盖在栅电极的侧壁上。

6. 发明授权

US09373548B2 CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layer 有权
标题翻译： CMOS电路具有覆盖在NMOS晶体管上并与压应力层的一部分重叠的拉伸应力层
公开(公告)号：US09373548B2
公开(公告)日：2016-06-21
申请号：US12199659
申请日：2008-08-27
申请人： Gen Pei , Scott D. Luning , Johannes van Meer
发明人： Gen Pei , Scott D. Luning , Johannes van Meer
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/84 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L29/7843
摘要： A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.
摘要翻译：提供了一种CMOS电路，其包括PMOS晶体管，在沟道宽度方向上与PMOS晶体管相邻的NMOS晶体管，覆盖PMOS晶体管的压应力衬垫以及覆盖NMOS晶体管的拉伸应力衬垫。压缩应力衬垫的一部分和拉伸应力衬垫的一部分处于堆叠构型，并且压应力衬垫和拉伸应力衬垫的重叠区域足以导致压缩应力衬垫中的增强的横向应力或拉伸应力衬垫。

7. 发明授权

US08617957B1 Fin bipolar transistors having self-aligned collector and emitter regions 失效
标题翻译：鳍状双极晶体管具有自对准的集电极和发射极区域
公开(公告)号：US08617957B1
公开(公告)日：2013-12-31
申请号：US13607877
申请日：2012-09-10
申请人： Josephine B Chang , Gen Pei Lauer , Isaac Lauer , Jeffrey W Sleight
发明人： Josephine B Chang , Gen Pei Lauer , Isaac Lauer , Jeffrey W Sleight
IPC分类号： H01L21/331
CPC分类号： H01L29/42304 , H01L29/1008 , H01L29/6625 , H01L29/66265 , H01L29/7317 , H01L29/735 , H01L29/785
摘要： A method for fabricating a bipolar transistor device. The method includes the steps of: providing a SOI substrate having a silicon layer thereon; patterning lithographically a fin hardmask on the silicon layer; placing a dummy contact line over a central portion of patterned fin hardmask; doping the collector/emitter regions; depositing a filler layer over the collector region and the emitter region; removing the dummy contact line to reveal a trench and the central portion of the patterned fin hardmask; forming fin-shaped base regions by removing, within the trench, a portion of the silicon layer not covered by the central portion of the patterned fin hardmask after the step of removing the dummy contact line; doping the fin-shaped base region; and forming a contact line by filling the trench with a contact line material over the fin-shaped base regions, where the collector/emitter regions are self-aligned with the contact line.
摘要翻译：一种制造双极晶体管器件的方法。该方法包括以下步骤：提供其上具有硅层的SOI衬底; 在硅层上平版印刷鳍状硬掩模; 将虚拟接触线放置在图案化翅片硬掩模的中心部分上; 掺杂集电极/发射极区域; 在所述集电极区域和所述发射极区域上沉积填充层; 去除虚拟接触线以露出沟槽和图案化散热片硬掩模的中心部分; 在除去虚拟接触线的步骤之后，通过在沟槽内去除未被图案化翅片硬掩模的中心部分覆盖的硅层的一部分来形成翅片形基底区域; 掺杂鳍片状基底区域; 以及通过在所述鳍状基极区域上的接触线材料填充所述沟槽而形成接触线，其中所述集电极/发射极区域与所述接触线自对准。

8. 发明授权

US07442601B2 Stress enhanced CMOS circuits and methods for their fabrication 有权
标题翻译：应力增强CMOS电路及其制造方法
公开(公告)号：US07442601B2
公开(公告)日：2008-10-28
申请号：US11532753
申请日：2006-09-18
申请人： Gen Pei , Scott D. Luning , Johannes van Meer
发明人： Gen Pei , Scott D. Luning , Johannes van Meer
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L29/7843
摘要： A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated by an isolation region. A compressive stress liner is deposited overlying the transistors and the isolation region and is etched to remove the compressive stress liner from the NMOS transistor and from a portion of the isolation region. A tensile stress liner is deposited overlying the transistors, the isolation region, and the compressive stress liner and is etched to remove a portion of the tensile stress liner overlying a portion of the compressive stress liner and to leave the tensile stress liner overlying the NMOS transistor, the isolation region, and a portion of the compressive stress liner.
摘要翻译：提供了一种应力增强CMOS电路及其制造方法。一种制造方法包括以下步骤：在沟道宽度方向上形成与NMOS晶体管相邻的NMOS晶体管和PMOS晶体管，PMOS晶体管和NMOS晶体管由隔离区隔开。压缩应力衬垫沉积在晶体管和隔离区上，并被蚀刻以从NMOS晶体管和隔离区的一部分去除压应力衬垫。拉伸应力衬垫沉积在晶体管，隔离区域和压缩应力衬垫上，并被蚀刻以去除覆盖压缩应力衬垫的一部分的拉伸应力衬垫的一部分，并且留下覆盖NMOS晶体管的拉伸应力衬垫，隔离区域和压缩应力衬垫的一部分。

9. 发明申请

US20130153972A1 V-Groove Source/Drain Mosfet and Process For Fabricating Same 有权
标题翻译： V型槽源/排水滤芯及其制造方法
公开(公告)号：US20130153972A1
公开(公告)日：2013-06-20
申请号：US13624251
申请日：2012-09-21
申请人： MICHAEL A. GUILLORN , GEN PEI LAUER , ISAAC LAUER , JEFFREY W. SLEIGHT
发明人： MICHAEL A. GUILLORN , GEN PEI LAUER , ISAAC LAUER , JEFFREY W. SLEIGHT
IPC分类号： H01L27/12
CPC分类号： H01L21/823425 , H01L21/823481 , H01L21/84 , H01L29/045 , H01L29/41733 , H01L29/458 , H01L29/66772
摘要： A structure includes a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate and a silicided source/drain region formed in a V-shaped groove between the first and second adjacent gate structures. The silicided source/drain region formed in the V-shaped groove extend substantially from an edge of the first gate structure to an opposing edge of the second gate structure.
摘要翻译：一种结构包括在衬底的硅表面上至少包含第一和第二相邻栅极结构的衬底和形成在第一和第二相邻栅极结构之间的V形沟槽中的硅化物源/漏极区。形成在V形槽中的硅化物源极/漏极区域基本上从第一栅极结构的边缘延伸到第二栅极结构的相对边缘。

10. 发明申请

US20110063918A1 IDENTIFYING AT-RISK DATA IN NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储中识别风险数据
公开(公告)号：US20110063918A1
公开(公告)日：2011-03-17
申请号：US12694118
申请日：2010-01-26
申请人： Gen Pei , Lanlan Gu , Nima Mokhlesi , Idan Alrod , Eran Sharon , Itshak Afriat
发明人： Gen Pei , Lanlan Gu , Nima Mokhlesi , Idan Alrod , Eran Sharon , Itshak Afriat
IPC分类号： G11C16/04 , G11C29/00
CPC分类号： G11C16/3418 , G06F11/1072
摘要： The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use.
摘要翻译：非易失性存储系统基于性能数据预测哪些块（或其他存储单元）将变坏。预测为坏的那些块中的用户数据可以被重新编程到其他块，并且预测为坏的块可以被进一步使用。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式