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1. 发明授权

US09373548B2 CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layer 有权
标题翻译： CMOS电路具有覆盖在NMOS晶体管上并与压应力层的一部分重叠的拉伸应力层
公开(公告)号：US09373548B2
公开(公告)日：2016-06-21
申请号：US12199659
申请日：2008-08-27
申请人： Gen Pei , Scott D. Luning , Johannes van Meer
发明人： Gen Pei , Scott D. Luning , Johannes van Meer
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/84 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L29/7843
摘要： A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.
摘要翻译：提供了一种CMOS电路，其包括PMOS晶体管，在沟道宽度方向上与PMOS晶体管相邻的NMOS晶体管，覆盖PMOS晶体管的压应力衬垫以及覆盖NMOS晶体管的拉伸应力衬垫。压缩应力衬垫的一部分和拉伸应力衬垫的一部分处于堆叠构型，并且压应力衬垫和拉伸应力衬垫的重叠区域足以导致压缩应力衬垫中的增强的横向应力或拉伸应力衬垫。

2. 发明授权

US07442601B2 Stress enhanced CMOS circuits and methods for their fabrication 有权
标题翻译：应力增强CMOS电路及其制造方法
公开(公告)号：US07442601B2
公开(公告)日：2008-10-28
申请号：US11532753
申请日：2006-09-18
申请人： Gen Pei , Scott D. Luning , Johannes van Meer
发明人： Gen Pei , Scott D. Luning , Johannes van Meer
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L29/7843
摘要： A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated by an isolation region. A compressive stress liner is deposited overlying the transistors and the isolation region and is etched to remove the compressive stress liner from the NMOS transistor and from a portion of the isolation region. A tensile stress liner is deposited overlying the transistors, the isolation region, and the compressive stress liner and is etched to remove a portion of the tensile stress liner overlying a portion of the compressive stress liner and to leave the tensile stress liner overlying the NMOS transistor, the isolation region, and a portion of the compressive stress liner.
摘要翻译：提供了一种应力增强CMOS电路及其制造方法。一种制造方法包括以下步骤：在沟道宽度方向上形成与NMOS晶体管相邻的NMOS晶体管和PMOS晶体管，PMOS晶体管和NMOS晶体管由隔离区隔开。压缩应力衬垫沉积在晶体管和隔离区上，并被蚀刻以从NMOS晶体管和隔离区的一部分去除压应力衬垫。拉伸应力衬垫沉积在晶体管，隔离区域和压缩应力衬垫上，并被蚀刻以去除覆盖压缩应力衬垫的一部分的拉伸应力衬垫的一部分，并且留下覆盖NMOS晶体管的拉伸应力衬垫，隔离区域和压缩应力衬垫的一部分。

3. 发明申请

US20080122002A1 STRESS ENHANCED CMOS CIRCUITS AND METHODS FOR THEIR FABRICATION 有权
标题翻译：应力增强CMOS电路及其制造方法
公开(公告)号：US20080122002A1
公开(公告)日：2008-05-29
申请号：US11532753
申请日：2006-09-18
申请人： Gen Pei , Scott D. Luning , Johannes van Meer
发明人： Gen Pei , Scott D. Luning , Johannes van Meer
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L29/7843
摘要： A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated by an isolation region. A compressive stress liner is deposited overlying the transistors and the isolation region and is etched to remove the compressive stress liner from the NMOS transistor and from a portion of the isolation region. A tensile stress liner is deposited overlying the transistors, the isolation region, and the compressive stress liner and is etched to remove a portion of the tensile stress liner overlying a portion of the compressive stress liner and to leave the tensile stress liner overlying the NMOS transistor, the isolation region, and a portion of the compressive stress liner.
摘要翻译：提供了一种应力增强CMOS电路及其制造方法。一种制造方法包括以下步骤：在沟道宽度方向上形成与NMOS晶体管相邻的NMOS晶体管和PMOS晶体管，PMOS晶体管和NMOS晶体管由隔离区隔开。压缩应力衬垫沉积在晶体管和隔离区上，并被蚀刻以从NMOS晶体管和隔离区的一部分去除压应力衬垫。拉伸应力衬垫沉积在晶体管，隔离区域和压缩应力衬垫上，并被蚀刻以去除覆盖压缩应力衬垫的一部分的拉伸应力衬垫的一部分，并且留下覆盖NMOS晶体管的拉伸应力衬垫，隔离区域和压缩应力衬垫的一部分。

4. 发明申请

US20110165739A1 ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBEDDED SIGE PFET EXTENSION 有权
标题翻译：具有增加的外延源和漏极和嵌入式信号扩展的超薄SOI CMOS
公开(公告)号：US20110165739A1
公开(公告)日：2011-07-07
申请号：US13052702
申请日：2011-03-21
申请人： Amlan Majumdar , Gen Pei , Zhibin Ren , Dinkar Singh , Jeffrey W. Sleight
发明人： Amlan Majumdar , Gen Pei , Zhibin Ren , Dinkar Singh , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.
摘要翻译：通过将嵌入的pFET SiGe扩展与升高的源极/漏极区域集成来提高超薄硅上氧化物（UTSOI）FET器件中的沟道载流子迁移率的方法。该方法包括选择性地生长pFET区域中的嵌入式SiGe（eSiGe）扩展，并在CMOS上形成无应力的升高的Si或SiGe源极/漏极（RSD）区域。 eSiGe延伸区增强了pFET通道中的空穴迁移率，并降低了pFET延伸中的电阻。无应变的升高的源极/漏极区域减小了两个UTSOI pFET和nFET中的接触电阻。

5. 发明授权

US08012820B2 Ultra-thin SOI CMOS with raised epitaxial source and drain and embedded SiGe PFET extension 有权
标题翻译：具有凸起的外延源和漏极和嵌入式SiGe PFET扩展的超薄SOI CMOS
公开(公告)号：US08012820B2
公开(公告)日：2011-09-06
申请号：US13052702
申请日：2011-03-21
申请人： Amlan Majumdar , Gen Pei , Zhibin Ren , Dinkar Singh , Jeffrey W. Sleight
发明人： Amlan Majumdar , Gen Pei , Zhibin Ren , Dinkar Singh , Jeffrey W. Sleight
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.
摘要翻译：通过将嵌入的pFET SiGe扩展与升高的源极/漏极区域集成来提高超薄硅上氧化物（UTSOI）FET器件中的沟道载流子迁移率的方法。该方法包括选择性地生长pFET区域中的嵌入式SiGe（eSiGe）扩展，并在CMOS上形成无应力的升高的Si或SiGe源极/漏极（RSD）区域。 eSiGe延伸区增强了pFET通道中的空穴迁移率，并降低了pFET延伸中的电阻。无应变的升高的源极/漏极区域减小了两个UTSOI pFET和nFET中的接触电阻。

6. 发明授权

US07816767B2 Negative differential resistance diode and SRAM utilizing such device 有权
标题翻译：负差动电阻二极管和SRAM采用这种器件
公开(公告)号：US07816767B2
公开(公告)日：2010-10-19
申请号：US12368775
申请日：2009-02-10
申请人： Gen Pei , Zoran Krivokapic
发明人： Gen Pei , Zoran Krivokapic
IPC分类号： H01L29/72
CPC分类号： H01L27/11 , H01L29/7391
摘要： A negative differential resistance (NDR) diode and a memory cell incorporating that NDR diode are provided. The NDR diode comprises a p-type germanium region in contact with an n-type germanium region and forming a germanium pn junction diode. A first gate electrode overlies the p-type germanium region, is electrically coupled to the n-type germanium region, and is configured for coupling to a first electrical potential. A second gate electrode overlies the n-type germanium region and is configured for coupling to a second electrical potential. A third electrode is electrically coupled to the p-type germanium region and may be coupled to the second gate electrode. A small SRAM cell uses two such NDR diodes with a single pass transistor.
摘要翻译：提供负差分电阻（NDR）二极管和包含该NDR二极管的存储单元。 NDR二极管包括与n型锗区接触并形成锗pn结二极管的p型锗区。第一栅电极覆盖在p型锗区上，电耦合到n型锗区，并且被配置为耦合到第一电位。第二栅电极覆盖在n型锗区上，并被配置成耦合到第二电位。第三电极电耦合到p型锗区域并且可以耦合到第二栅电极。一个小的SRAM单元使用两个这样的NDR二极管与单通道晶体管。

7. 发明授权

US07416931B2 Methods for fabricating a stress enhanced MOS circuit 有权
标题翻译：制造应力增强型MOS电路的方法
公开(公告)号：US07416931B2
公开(公告)日：2008-08-26
申请号：US11466383
申请日：2006-08-22
申请人： Gen Pei
发明人： Gen Pei
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/66545 , H01L29/66659 , H01L29/7843
摘要： Methods are provided for fabricating a stress enhanced MOS circuit. One method comprises the steps of depositing a stressed material overlying a semiconductor substrate and patterning the stressed material to form a stressed dummy gate electrode overlying a channel region in the semiconductor substrate so that the stressed dummy gate induces a stress in the channel region. Regions of the semiconductor substrate adjacent the channel are processed to maintain the stress to the channel region and the stressed dummy gate electrode is replaced with a permanent gate electrode.
摘要翻译：提供了制造应力增强型MOS电路的方法。一种方法包括以下步骤：沉积覆盖在半导体衬底上的应力材料，并对应力材料进行图案化以形成覆盖在半导体衬底中的沟道区域上的应力虚拟栅电极，使得应力虚拟栅极在沟道区域中产生应力。处理与沟道相邻的半导体衬底的区域以保持对沟道区的应力，并且用永久栅电极代替应力的虚拟栅电极。

8. 发明申请

US20080038886A1 STRESS ENHANCED MOS CIRCUITS AND METHODS FOR THEIR FABRICATION 有权
标题翻译：应力增强MOS电路及其制造方法
公开(公告)号：US20080038886A1
公开(公告)日：2008-02-14
申请号：US11464090
申请日：2006-08-11
申请人： Gen Pei
发明人： Gen Pei
IPC分类号： H01L21/8234
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/823807 , H01L21/84 , H01L29/4925 , H01L29/66772 , H01L29/7845 , H01L29/78654
摘要： A stress enhanced MOS circuit and methods for its fabrication are provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness overlying the layer of polycrystalline silicon. A stress liner overlies the side walls of the gate electrode.
摘要翻译：提供一种应力增强型MOS电路及其制造方法。应力增强型MOS电路包括半导体衬底和覆盖半导体衬底的栅极绝缘体。栅电极覆盖栅极绝缘体; 栅电极具有侧壁并且包括具有与栅极绝缘体接触的第一厚度的多晶硅层和具有大于覆盖多晶硅层的第一厚度的第二厚度的导电应力材料层。应力衬垫覆盖在栅电极的侧壁上。

9. 发明授权

US08400854B2 Identifying at-risk data in non-volatile storage 有权
标题翻译：识别非易失性存储中的风险数据
公开(公告)号：US08400854B2
公开(公告)日：2013-03-19
申请号：US12694118
申请日：2010-01-26
申请人： Gen Pei , Lanlan Gu , Nima Mokhlesi , Idan Alrod , Eran Sharon , Itshak Afriat
发明人： Gen Pei , Lanlan Gu , Nima Mokhlesi , Idan Alrod , Eran Sharon , Itshak Afriat
IPC分类号： G11C29/04 , G11C29/06
CPC分类号： G11C16/3418 , G06F11/1072
摘要： The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use.
摘要翻译：非易失性存储系统基于性能数据预测哪些块（或其他存储单元）将变坏。预测为坏的那些块中的用户数据可以被重新编程到其他块，并且预测为坏的块可以被进一步使用。

10. 发明授权

US07943999B2 Stress enhanced MOS circuits 有权
标题翻译：应力增强MOS电路
公开(公告)号：US07943999B2
公开(公告)日：2011-05-17
申请号：US12208196
申请日：2008-09-10
申请人： Gen Pei
发明人： Gen Pei
IPC分类号： H01L27/08
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/823807 , H01L21/84 , H01L29/4925 , H01L29/66772 , H01L29/7845 , H01L29/78654
摘要： A stress enhanced MOS circuit is provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness overlying the layer of polycrystalline silicon. A stress liner overlies the side walls of the gate electrode.
摘要翻译：提供了一种应力增强型MOS电路。应力增强型MOS电路包括半导体衬底和覆盖半导体衬底的栅极绝缘体。栅电极覆盖栅极绝缘体; 栅电极具有侧壁并且包括具有与栅极绝缘体接触的第一厚度的多晶硅层和具有大于覆盖多晶硅层的第一厚度的第二厚度的导电应力材料层。应力衬垫覆盖在栅电极的侧壁上。

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