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1. 发明授权

US5870031A Full-wave rectifier and method of operation for a recognition system 失效
标题翻译：全波整流器及识别系统的操作方法
公开(公告)号：US5870031A
公开(公告)日：1999-02-09
申请号：US792643
申请日：1997-01-31
申请人： Ulrich Kaiser , Harald Parzhuber
发明人： Ulrich Kaiser , Harald Parzhuber
IPC分类号： G06K19/07 , G07C9/00 , H02M7/219 , H04Q5/22 , H02M1/20 , H03K5/00 , H04L13/10
CPC分类号： H02M7/219 , G06K19/0723 , G07C9/00309 , H02M2007/2195 , Y02B70/1408
摘要： A full-wave rectifier circuit (70) includes a first transistor (N1) and a second transistor (N2) in combination to form a first transistor pair (N1 and N2) for minimizing the voltage drop between ground (88) and the transponder substrates. A third transistor (P1) and a fourth transistor (P2) operate in combination to form a second transistor pair (P1 and P2) for minimizing the voltage drop between the alternating current peak voltage (118 and 120) and the output voltage (V.sub.DD) of the full-wave rectifier (70). The first transistor pair (N1 and N2) and second transistor pair (P1 and P2) are controlled by alternating current voltage input signals (118 and 120). A series regulator circuit (70) decouples the first transistor pair (N1 and N2) and the second transistor pair (P1 and P2) from capacitive loads (C1 and C2) of the full-duplex transponder circuitry (14).
摘要翻译：全波整流电路（70）包括组合的第一晶体管（N1）和第二晶体管（N2），以形成第一晶体管对（N1和N2），用于最小化接地（88）和应答器基板。第三晶体管（P1）和第四晶体管（P2）组合工作以形成用于最小化交流电压峰值电压（118和120）与输出电压（VDD）之间的电压降的第二晶体管对（P1和P2）的全波整流器（70）。第一晶体管对（N1和N2）和第二晶体管对（P1和P2）由交流电压输入信号（118和120）控制。串联稳压器电路（70）将第一晶体管对（N1和N2）和第二晶体管对（P1和P2）与全双工转发器电路（14）的容性负载（C1和C2）分离。

2. 发明授权

US07605664B2 All digital phase locked loop system and method 有权
标题翻译：所有数字锁相环系统及方法
公开(公告)号：US07605664B2
公开(公告)日：2009-10-20
申请号：US11624149
申请日：2007-01-17
申请人： Harald Sandner , Harald Parzhuber
发明人： Harald Sandner , Harald Parzhuber
IPC分类号： H03L7/085
CPC分类号： H03L7/08 , H03L2207/50
摘要： An all digital PLL system generates an analog oscillator signal at intermediate frequencies to achieve averaged oscillator frequencies at an extremely high frequency resolution. The PLL system includes a digitally controlled oscillator (10) with a digital control input and an analog signal output, and a feedback loop with a digital loop filter (16) for generating a digital control signal for the digitally controlled oscillator (10). The digital loop filter (16) has a first output providing an integer part (nint) of the digital control signal and a second output providing a fractional part (nΣΔ) of the digital control signal. A sigma-delta modulator (14) has an input connected to the second output of the digital loop filter (16) and an output providing a one-bit digital output signal (ΣΔ), and a digital adder (12) has a first input connected to the first output of the digital loop filter (16), a second input connected to the output of the sigma-delta modulator (14), and an output connected to the digital control input of the digitally controlled oscillator (10). The output of the sigma-delta modulator (14) modulates the least significant bits from the first output of the digital loop filter (16).
摘要翻译：全数字PLL系统在中频产生模拟振荡器信号，以极高频率分辨率实现平均振荡器频率。 PLL系统包括具有数字控制输入和模拟信号输出的数字控制振荡器（10）和具有数字环路滤波器（16）的反馈回路，用于产生数字控制振荡器（10）的数字控制信号。数字环路滤波器（16）具有提供数字控制信号的整数部分（nint）的第一输出和提供数字控制信号的小数部分（nSigmaDelta）的第二输出。 Σ-Δ调制器（14）具有连接到数字环路滤波器（16）的第二输出的输入端和提供一比特数字输出信号（SigmaDelta）的输出，数字加法器（12）具有第一输入连接到数字环路滤波器（16）的第一输出，连接到Σ-Δ调制器（14）的输出端的第二输入端和连接到数字控制振荡器（10）的数字控制输入端的输出端。 Σ-Δ调制器（14）的输出调制来自数字环路滤波器（16）的第一输出的最低有效位。

3. 发明申请

US20070200638A1 ALL DIGITAL PHASE LOCKED LOOP SYSTEM AND METHOD 有权
标题翻译：所有数字相位锁定系统和方法
公开(公告)号：US20070200638A1
公开(公告)日：2007-08-30
申请号：US11624149
申请日：2007-01-17
申请人： HARALD SANDNER , HARALD PARZHUBER
发明人： HARALD SANDNER , HARALD PARZHUBER
IPC分类号： H03L7/00
CPC分类号： H03L7/08 , H03L2207/50
摘要： An all digital PLL system generates an analog oscillator signal at intermediate frequencies to achieve averaged oscillator frequencies at an extremely high frequency resolution. The PLL system includes a digitally controlled oscillator (10) with a digital control input and an analog signal output, and a feedback loop with a digital loop filter (16) for generating a digital control signal for the digitally controlled oscillator (10). The digital loop filter (16) has a first output providing an integer part (nint) of the digital control signal and a second output providing a fractional part (nΣΔ) of the digital control signal. A sigma-delta modulator (14) has an input connected to the second output of the digital loop filter (16) and an output providing a one-bit digital output signal (ΣΔ), and a digital adder (12) has a first input connected to the first output of the digital loop filter (16), a second input connected to the output of the sigma-delta modulator (14), and an output connected to the digital control input of the digitally controlled oscillator (10). The output of the sigma-delta modulator (14) modulates the least significant bits from the first output of the digital loop filter (16).
摘要翻译：全数字PLL系统在中频产生模拟振荡器信号，以极高频率分辨率实现平均振荡器频率。 PLL系统包括具有数字控制输入和模拟信号输出的数字控制振荡器（10）和具有数字环路滤波器（16）的反馈回路，用于产生数字控制振荡器（10）的数字控制信号。数字环路滤波器（16）具有第一输出，提供数字控制信号的整数部分（n _{int），第二输出提供小数部分（nSigmaDelta）的数字控制信号。 Σ-Δ调制器（14）具有连接到数字环路滤波器（16）的第二输出的输入端和提供一比特数字输出信号（SigmaDelta）的输出，数字加法器（12）具有第一输入连接到数字环路滤波器（16）的第一输出，连接到Σ-Δ调制器（14）的输出端的第二输入端和连接到数字控制振荡器（10）的数字控制输入端的输出端。 Σ-Δ调制器（14）的输出调制来自数字环路滤波器（16）的第一输出的最低有效位。}

4. 发明授权

US06806783B2 Circuit assembly for generating RF oscillation plucking pulses 有权
标题翻译：用于产生RF振荡采摘脉冲的电路组件
公开(公告)号：US06806783B2
公开(公告)日：2004-10-19
申请号：US10081049
申请日：2002-02-20
申请人： Adolf Baumann , Harald Parzhuber
发明人： Adolf Baumann , Harald Parzhuber
IPC分类号： H03B100
CPC分类号： G06K19/0701 , G06K19/0723
摘要： In a circuit assembly for generating pulses sustaining or “plucking” RF oscillations in a resonant circuit (12) of transponder (10) having no battery power supply in which the supply voltage needed for its operation is obtained from a RF carrier oscillation pulse defined in time exciting the resonant circuit into oscillation and used to charge a storage element whose charging voltage forms the supply voltage, a plucking pulse is generated every time the amplitude of the RF oscillations drops below a defined threshold value and its momentary value is in a defined relationship to a reference voltage (VPEAK) changing in time as the charging voltage of a capacitor (70). A switch (24) is provided which can be switched on for the duration of the plucking pulse (PLUCK) for connecting the storage element (20) to the resonant circuit (12). A closed control loop (34, 38) is provided which varies the slope of the reference voltage curve between two plucking (PLUCK) pulses in the direction of maintaining the predefined relationship between the momentary value of the RF oscillations and the reference voltage.
摘要翻译：在用于产生在没有电池电源的应答器（10）的谐振电路（12）中维持或“拔除”射频振荡的脉冲的电路组件中，其中从其中定义的RF载波振荡脉冲获得其操作所需的电源电压时间激励谐振电路进入振荡，并用于对其充电电压形成电源电压的存储元件充电，每当RF振荡的幅度下降到低于定义的阈值并且其瞬时值处于确定的关系中时，产生拔除脉冲到作为电容器（70）的充电电压的时间变化的参考电压（VPEAK）。提供开关（24），其可以在用于将存储元件（20）连接到谐振电路（12）的拔除脉冲（PLUCK）的持续时间内接通。提供一个闭合的控制回路（34,38），其在维持RF振荡的瞬时值与参考电压之间的预定关系的方向上改变两个采摘（PLUCK）脉冲之间的参考电压曲线的斜率。

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