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1. 发明授权

US06951811B2 Method of producing vias and other conductor parts on an electrode terminal forming surface of a semiconductor wafer 有权
标题翻译：在半导体晶片的电极端子形成表面上制造通路和其它导体部件的方法
公开(公告)号：US06951811B2
公开(公告)日：2005-10-04
申请号：US10828328
申请日：2004-04-21
申请人： Haruo Sorimachi
发明人： Haruo Sorimachi
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L23/12 , H01L23/31 , H01L21/4763
CPC分类号： H01L24/12 , H01L23/3114 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05647 , H01L2224/1147 , H01L2224/13099 , H01L2224/82039 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要： A method of production of a semiconductor device able to utilize a conventional production system for a resin board to thereby produce a wafer level package without increasing the production cost, comprising electrolessly plating the electrode terminals to cover the surfaces of the electrode terminals by a protective film protecting the electrode terminals from laser beams; grinding the back side of the semiconductor wafer to reduce the thickness of the semiconductor wafer before or after forming the protective film; covering the entirety of the electrode terminal forming surface and back side of the semiconductor wafer, having the electrode terminals covered by a protective film and processed to reduce the thickness of the semiconductor wafer, by a resin to form a laminate; and focusing a laser beam toward the electrode terminal forming surface of the semiconductor wafer from outside the laminate to form via holes with the protective film exposed at their bottom surfaces, then filling the via holes by electroplating to form the conductor parts.
摘要翻译：一种制造半导体器件的方法，该半导体器件能够利用传统的树脂板生产系统，从而生产晶片级封装而不增加生产成本，包括用电极端子无电镀以覆盖电极端子表面的保护膜保护电极端子免受激光束的影响; 研磨半导体晶片的背面以在形成保护膜之前或之后减小半导体晶片的厚度; 覆盖半导体晶片的整个电极端子形成表面和背面，其中电极端子由保护膜覆盖并被处理以减小半导体晶片的厚度，由树脂形成层压体; 并且将激光束从层叠体的外部聚焦到半导体晶片的电极端子形成表面，以形成通孔，其中保护膜在其底表面暴露，然后通过电镀填充通孔以形成导体部分。

2. 发明授权

US08355262B2 Electronic component built-in substrate and method of manufacturing electronic component built-in substrate 有权
标题翻译：电子元件内置基板和电子元器件内置基板的制造方法
公开(公告)号：US08355262B2
公开(公告)日：2013-01-15
申请号：US12000729
申请日：2007-12-17
申请人： Akinobu Inoue , Haruo Sorimachi
发明人： Akinobu Inoue , Haruo Sorimachi
IPC分类号： H05K1/18
CPC分类号： H01L23/5389 , H01L21/4857 , H01L23/49833 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/05554 , H01L2224/05624 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48465 , H01L2224/48599 , H01L2224/48992 , H01L2224/49175 , H01L2224/49176 , H01L2224/73204 , H01L2224/73265 , H01L2224/85011 , H01L2224/8592 , H01L2225/0651 , H01L2225/0652 , H01L2225/06558 , H01L2225/06586 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30107 , H05K1/185 , H05K3/4614 , Y10T29/49124 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： An electronic component is provided between at least two wiring boards. An electrode of the electronic component is electrically connected to at least one of the wiring boards. Also, the wiring boards and are electrically connected to each other. Additionally, the gap between the wiring boards and is sealed with a resin. The electronic component built-in substrate is featured in that a bonding pad formed on one of the wiring boards and is electrically connected to an electrode of the electronic component by a bonding wire, and that at least a connection portion between the electrode of the electronic component and the bonding wire is coated with a protection material.
摘要翻译：在至少两个布线板之间设置电子部件。电子部件的电极与至少一个布线板电连接。而且，布线板彼此电连接。此外，布线板之间的间隙用树脂密封。电子部件内置基板的特征在于，形成在一个布线基板上的接合焊盘通过接合线电连接到电子部件的电极，并且至少在电子部件的电极之间的连接部组件和接合线涂有保护材料。

3. 发明授权

US06791186B2 Mounting substrate and structure having semiconductor element mounted on substrate 有权
标题翻译：具有安装在基板上的半导体元件的安装基板和结构
公开(公告)号：US06791186B2
公开(公告)日：2004-09-14
申请号：US10127640
申请日：2002-04-22
申请人： Haruo Sorimachi , Yoshihiro Yoneda
发明人： Haruo Sorimachi , Yoshihiro Yoneda
IPC分类号： H01L2348
CPC分类号： H01L23/49822 , H01L23/49838 , H01L24/81 , H01L2224/1134 , H01L2224/13099 , H01L2224/13144 , H01L2224/16238 , H01L2224/81191 , H01L2224/81395 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/00015 , H01L2224/0401
摘要： A mounting substrate on which a semiconductor element is to be mounted by flip-chip bonding, the semiconductor element having a surface on which a plurality of electrode terminals are arranged in a line, each of said electrode terminals having a protruded electrode formed thereon, wherein the surface of the mounting substrate on which the semiconductor element is to be mounted is provided with a protective film having an opening corresponding to an area of the semiconductor element where the protruded electrodes are located, a plurality of connection electrodes being arranged in the opening, the connection electrodes being provided with a solder for bonding it to the protruded electrodes, and being arranged at the same interval as that of the protruded electrodes, and each of the connection electrodes being connected to a wiring pattern of the mounting substrate, and wherein the length of a portion of the connection electrode from the center of the opening to the end thereof that is not connected with the wiring pattern is 150 &mgr;m or larger. A structure having a semiconductor element mounted on the substrate is also disclosed.
摘要翻译：一种通过倒装芯片接合将半导体元件安装在其上的安装基板，该半导体元件具有多个电极端子排列成一行的表面，每个所述电极端子上形成有突起电极，其中，安装有半导体元件的安装基板的表面设置有保护膜，该保护膜具有对应于突起电极所在的半导体元件的区域的开口，多个连接电极布置在开口中，连接电极设置有用于将其焊接到突出电极的焊料，并且以与突出电极相同的间隔布置，并且每个连接电极连接到安装基板的布线图案，并且其中连接电极的一部分的长度从开口的中心到其末端为no t接线图为150 mum以上。还公开了具有安装在基板上的半导体元件的结构。

4. 发明申请

US20080174978A1 Electronic component built-in substrate and method of manufacturing electronic component built-in substrate 有权
标题翻译：电子元件内置基板和电子元器件内置基板的制造方法
公开(公告)号：US20080174978A1
公开(公告)日：2008-07-24
申请号：US12000729
申请日：2007-12-17
申请人： Akinobu Inoue , Haruo Sorimachi
发明人： Akinobu Inoue , Haruo Sorimachi
IPC分类号： H05K1/14 , H05K3/00
CPC分类号： H01L23/5389 , H01L21/4857 , H01L23/49833 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/05554 , H01L2224/05624 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48465 , H01L2224/48599 , H01L2224/48992 , H01L2224/49175 , H01L2224/49176 , H01L2224/73204 , H01L2224/73265 , H01L2224/85011 , H01L2224/8592 , H01L2225/0651 , H01L2225/0652 , H01L2225/06558 , H01L2225/06586 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30107 , H05K1/185 , H05K3/4614 , Y10T29/49124 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： It is an electronic component built-in substrate 100 configured as follows. That is, an electronic component 30 is provided between at least two wiring boards 10 and 20. An electrode 34 of the electronic component 30 is electrically connected to at least one of the wiring boards. Also, the wiring boards 10 and 20 are electrically connected to each other. Additionally, the gap between the wiring boards 10 and 20 is sealed with a resin. The electronic component built-in substrate 100 is featured in that a bonding pad 12 formed on one of the wiring boards 10 and 20 is electrically connected to an electrode 32 of the electronic component 30 by a bonding wire 60, and that at least a connection portion between the electrode 32 of the electronic component 30 and the bonding wire 60 is coated with a protection material 70.
摘要翻译：它是如下配置的电子部件内置基板100。也就是说，电子部件30设置在至少两个接线板10和20之间。电子部件30的电极34与至少一方的布线基板电连接。此外，布线板10和20彼此电连接。另外，用树脂密封布线板10和20之间的间隙。电子部件内置基板100的特征在于，形成在一个布线基板10,20上的接合焊盘12通过接合线60与电子部件30的电极32电连接，至少连接电子部件30的电极32与接合线60之间的部分涂覆有保护材料70。

5. 发明申请

US20050258853A1 Semiconductor device and interposer 有权
标题翻译：半导体器件和内插器
公开(公告)号：US20050258853A1
公开(公告)日：2005-11-24
申请号：US10521195
申请日：2004-04-15
申请人： Haruo Sorimachi
发明人： Haruo Sorimachi
IPC分类号： H01L23/31 , H01L23/58 , H01L25/065 , H01L25/10 , G01R31/02
CPC分类号： H01L24/05 , H01L22/32 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06555 , H01L2225/06558 , H01L2225/06568 , H01L2225/06582 , H01L2225/06596 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device characterized in that connection pads for wire bonding are arranged at peripheral regions of an electrode terminal formation surface of a semiconductor chip, test pads for testing the semiconductor chip are arranged in an inside region surrounded by said peripheral regions of said electrode terminal formation surface, and a plurality of rewiring patterns extend from the peripheral regions to said inside region of said electrode terminal formation surface and the individual rewiring patterns connect the individual electrode terminals and the corresponding connection pads and test pads.
摘要翻译：一种半导体器件，其特征在于，用于引线键合的连接焊盘被布置在半导体芯片的电极端子形成表面的外围区域处，用于测试半导体芯片的测试焊盘被布置在由所述电极端子形成的所述周边区域包围的内部区域中表面，并且多个重新布线图案从周边区域延伸到所述电极端子形成表面的所述内部区域，并且各个重新布线图案连接各个电极端子和相应的连接焊盘和测试焊盘。

6. 发明授权

US5432675A Multi-chip module having thermal contacts 失效
标题翻译：具有热触点的多芯片模块
公开(公告)号：US5432675A
公开(公告)日：1995-07-11
申请号：US151871
申请日：1993-11-15
申请人： Haruo Sorimachi , Kiyotaka Seyama , Makoto Sumiyoshi , Kazuaki Satoh
发明人： Haruo Sorimachi , Kiyotaka Seyama , Makoto Sumiyoshi , Kazuaki Satoh
IPC分类号： H01L23/367 , H01L23/498 , H01L23/538 , H05K7/20
CPC分类号： H01L23/49894 , H01L23/3677 , H01L23/49866 , H01L23/538 , H01L2224/16 , H01L2224/48091 , H01L2924/15312 , H01L2924/1532 , H01L2924/16195 , H01L2924/19107 , H01L2924/3011
摘要： A multi-chip module (MCM) having semiconductor chips on a top surface of multi-layered interconnection circuits formed on a planar surface of a substrate including: (a) multi-layered interconnection circuits comprising alternatively laminated interconnection layers with insulating layers, and thermal contacts, each of the thermal contacts comprising successively laminated interconnection layers on a bottom and on side-walls of a vertical hole penetrating a plurality of the insulating layers, and a thermal conductor filling the vertical hole on the successively laminated interconnection layers, and (b) a plurality of the semiconductor chips attached to the thermal conductor. In a preferred embodiment, a V-shaped vertical hole is formed in the insulating layers of polyimide for a thermal contact, copper films are successively laminated thereon, unpatterned copper and gold films are deposited thereon, and the entire surface of the metal film including the hole is coated by a silver-powder containing epoxy film, to which semiconductor chips are adhered.
摘要翻译：一种多芯片模块（MCM），其在多层互连电路的顶面上形成半导体芯片，所述多层布线电路形成在基板的平面上，所述多层布线电路的平面表面包括：（a）多层互连电路，触点，每个热触头包括穿透多个绝缘层的垂直孔的底部和侧壁上的相继层压的互连层，以及填充连续层压的互连层上的垂直孔的热导体，和（b ）附接到热导体的多个半导体芯片。在优选实施例中，在聚酰亚胺的绝缘层中形成V形垂直孔用于热接触，铜膜依次层压在其上，未图案化的铜和金膜沉积在其上，金属膜的整个表面包括孔被含有银粉的环氧树脂膜涂覆，半导体芯片被粘附到其上。

7. 发明授权

US4595823A Thermal printing head with an anti-abrasion layer and method of fabricating the same 失效
标题翻译：具有抗磨损层的热敏打印头及其制造方法
公开(公告)号：US4595823A
公开(公告)日：1986-06-17
申请号：US590887
申请日：1984-03-19
申请人： Haruo Sorimachi , Kiyoshi Satoh , Takumi Suzuki
发明人： Haruo Sorimachi , Kiyoshi Satoh , Takumi Suzuki
IPC分类号： B41J2/315 , B41J2/335 , H01L49/00 , G01D15/10
CPC分类号： B41J2/3353 , B41J2/3355 , B41J2/3357
摘要： Cracks in an Ta.sub.2 O.sub.5 anti-abrasion layer of a thermal printing head resulting from the crystallization of the Ta.sub.2 O.sub.5 in the layer, are suppressed by the addition of SiO.sub.2 to the layer. The anti-abrasion layer is provided as a uniform mixture of Ta.sub.2 O.sub.5 and SiO.sub.2 throughout the layer by sputtering a target composed of a mixture containing tantalum and silicon ingredients onto an antioxidation layer. The thermal printing head is also subjected to annealing to stabilize the resistivity of the heating elements.
摘要翻译：通过在层中添加SiO 2来抑制由层中的Ta 2 O 5的结晶产生的热打印头的Ta 2 O 5耐磨层中的裂纹。通过将由含有钽和硅成分的混合物组成的靶溅射到抗氧化层上，将抗磨层作为整个层中的Ta 2 O 5和SiO 2的均匀混合物提供。热敏打印头也进行退火以稳定加热元件的电阻率。

8. 发明授权

US07342248B2 Semiconductor device and interposer 有权
标题翻译：半导体器件和内插器
公开(公告)号：US07342248B2
公开(公告)日：2008-03-11
申请号：US10521195
申请日：2004-04-15
申请人： Haruo Sorimachi
发明人： Haruo Sorimachi
IPC分类号： H01L23/58
CPC分类号： H01L24/05 , H01L22/32 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06555 , H01L2225/06558 , H01L2225/06568 , H01L2225/06582 , H01L2225/06596 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device characterized in that connection pads for wire bonding are arranged at peripheral regions of an electrode terminal formation surface of a semiconductor chip, test pads for testing the semiconductor chip are arranged in an inside region surrounded by said peripheral regions of said electrode terminal formation surface, and a plurality of rewiring patterns extend from the peripheral regions to said inside region of said electrode terminal formation surface and the individual rewiring patterns connect the individual electrode terminals and the corresponding connection pads and test pads.
摘要翻译：一种半导体器件，其特征在于，用于引线键合的连接焊盘被布置在半导体芯片的电极端子形成表面的外围区域处，用于测试半导体芯片的测试焊盘被布置在由所述电极端子形成的所述周边区域包围的内部区域中表面，并且多个重新布线图案从周边区域延伸到所述电极端子形成表面的所述内部区域，并且各个重新布线图案连接各个电极端子和相应的连接焊盘和测试焊盘。

9. 发明授权

US4689638A Thermal recording head and process for manufacturing wiring substrate therefor 失效
标题翻译：热敏记录头及其制造布线基板的工艺
公开(公告)号：US4689638A
公开(公告)日：1987-08-25
申请号：US712713
申请日：1985-03-18
申请人： Toshio Matsuzaki , Haruo Sorimachi , Kiyoshi Satoh , Takumi Suzuki , Takeshi Sugii
发明人： Toshio Matsuzaki , Haruo Sorimachi , Kiyoshi Satoh , Takumi Suzuki , Takeshi Sugii
IPC分类号： H04N1/00 , B41J2/335 , G01D15/10
CPC分类号： B41J2/3351 , B41J2/33515 , B41J2/33525 , B41J2/3353 , B41J2/33535 , B41J2/33545 , B41J2/3355 , B41J2/3357 , B41J2/3359
摘要： A thermal recording head comprising an insulating substrate which has thereon a heat generating resistor pattern made of a thin-film resistor, an electrode pattern having a common power supply electrode pattern portion and a common grounded electrode pattern portion, for supplying the power to the resistor pattern, and a controlling electrode pattern portion, and switching elements for controlling the supply of the power to the resistor pattern. The electrode pattern is made of a thick-film copper paste by a printing process. The operation of the switching elements is controlled by the controlling electrode pattern portion.Also disclosed is a process for manufacturing a wiring substrate for a thermal recording head.
摘要翻译：一种热敏记录头，包括绝缘基板，其上具有由薄膜电阻器制成的发热电阻器图案，具有公共电源电极图案部分和公共接地电极图案部分的电极图案，用于向电阻器图案和控制电极图案部分，以及用于控制向电阻器图案供电的开关元件。电极图案通过印刷方法由厚膜铜浆制成。开关元件的操作由控制电极图案部分控制。还公开了一种用于制造用于热敏记录头的布线基板的方法。

10. 发明授权

US4446355A Crossover construction of thermal-head and method of manufacturing same 失效
标题翻译：交叉结构热头及其制造方法相同
公开(公告)号：US4446355A
公开(公告)日：1984-05-01
申请号：US351284
申请日：1982-02-22
申请人： Kiyoshi Sato , Minoru Terashima , Haruo Sorimachi , Toshiaki Naka , Takeo Kanno , Fumiaki Yamada
发明人： Kiyoshi Sato , Minoru Terashima , Haruo Sorimachi , Toshiaki Naka , Takeo Kanno , Fumiaki Yamada
IPC分类号： B41J2/345 , H01L49/00 , H01L49/02 , H05K3/46 , H05B3/00 , B41J3/20 , G01D15/10
CPC分类号： H01L49/02 , B41J2/345 , H05K3/4664 , Y10T29/49083 , Y10T29/49099
摘要： A crossover construction of a thermal-head is which the thermal-head comprises: a substrate of insulating material; a plurality of heat elements disposed side by side in one row on said substrate; a plurality of lower thin film conductor patterns each of which connects to each of said heat elements and extends in direction X; an insulating layer disposed over said lower conductors; a plurality of upper conductor patterns disposed in parallel in another direction Y on said insulating layer so as to form a crossover on said substrate, said upper and lower conductors being selectively connected together through openings of said insulating layer, wherein said insulating layer and said upper conductors comprise printed and cured paste of insulating material and conductive material, respectively, each paste being of the low temperature curing type which can be cured at a temperature low enough not to affect the resistance of said thin film lower conductors, and a metallic layer of low resistance is coated on each of said upper conductors.
摘要翻译：热头的交叉结构是热头包括：绝缘材料的基底; 在所述基板上一行排列并列设置的多个加热元件; 多个下部薄膜导体图案，其各自连接到每个所述加热元件并沿方向X延伸; 设置在所述下导体上的绝缘层; 在所述绝缘层上沿另一方向Y平行设置的多个上导体图形，以便在所述衬底上形成交叉，所述上导体和下导体通过所述绝缘层的开口选择性地连接在一起，其中所述绝缘层和所述上层导体分别包括绝缘材料和导电材料的印刷和固化糊料，每种糊料是低温固化型，其可以在足够低的温度下固化，不会影响所述薄膜下导体的电阻，并且金属层在每个所述上导体上涂覆低电阻。

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