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1. 发明申请

US20100315860A1 INTEGRATED CIRCUIT WITH A MEMORY MATRIX WITH A DELAY MONITORING COLUMN 有权
标题翻译：具有延迟监测列的记忆矩阵的集成电路
公开(公告)号：US20100315860A1
公开(公告)日：2010-12-16
申请号：US12866876
申请日：2009-02-09
申请人： Hendricus J. M. Veendrick , Harold G. P. Benten , Agnese A. M. Bargagli-Stoffi , Patrick Van de Steeg
发明人： Hendricus J. M. Veendrick , Harold G. P. Benten , Agnese A. M. Bargagli-Stoffi , Patrick Van de Steeg
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , G11C11/41 , G11C11/413 , G11C29/50 , G11C29/50012 , H01L27/0207 , H01L27/105 , H01L27/11
摘要： An integrated circuit has a matrix of rows and columns of cells (10, 18, 19), each cell (10, 18, 19) comprising a first inverter (100) and a second inverter (102). First columns have a bit-line (12a,b), the first inverter (100) and the second inverter (102) in each cell of the first columns being cross-coupled to each other and coupled to bit-line (12a,b) of the associated first column. A further column is provided in the matrix with bit line fragments (16) that are mutually disconnected. Delays are monitored by coupling at least the first inverters (100) of cells in respective pairs of rows in series via the bit-line fragments and measuring a delay during signal propagation through the series connection, for example by in corporating the series of inverters in a ring oscillator.
摘要翻译：集成电路具有单元行（10,18,19）的行和列的矩阵，每个单元（10,18,19）包括第一反相器（100）和第二反相器（102）。第一列具有位线（12a，b），第一列的每个单元中的第一反相器（100）和第二反相器（102）彼此交叉耦合并耦合到位线（12a，b））相关联的第一列。在矩阵中提供另一列，其中相互断开的位线片段（16）。通过经由位线片段将至少串联的各对行中的单元的至少第一反相器（100）耦合起来来监视延迟，并且例如通过将串联连接中的一系列逆变器合并来测量在串联连接期间的信号传播期间的延迟环形振荡器。

2. 发明申请

US20110156804A1 VOLTAGE REFERENCE CIRCUIT FOR LOW SUPPLY VOLTAGES 有权
标题翻译：低电压电压参考电路
公开(公告)号：US20110156804A1
公开(公告)日：2011-06-30
申请号：US12651408
申请日：2009-12-31
申请人： Marcel J. M. Pelgrom , Hendricus J. M. Veendrick , Victor Zieren
发明人： Marcel J. M. Pelgrom , Hendricus J. M. Veendrick , Victor Zieren
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A voltage reference circuit and method for generating a reference voltage using the circuit uses a comparison of the voltages on first and second nodes of a diode resistor network to produce a comparison signal, which is then used to increase the voltage on an output of a charge pump to generate the reference voltage.
摘要翻译：使用该电路产生参考电压的电压参考电路和方法使用二极管电阻网络的第一和第二节点上的电压的比较来产生比较信号，然后将其用于增加电荷输出上的电压泵产生参考电压。

3. 发明授权

US08022752B2 Voltage reference circuit for low supply voltages 有权
标题翻译：用于低电源电压的电压参考电路
公开(公告)号：US08022752B2
公开(公告)日：2011-09-20
申请号：US12651408
申请日：2009-12-31
申请人： Marcel J. M. Pelgrom , Hendricus J. M. Veendrick , Victor Zieren
发明人： Marcel J. M. Pelgrom , Hendricus J. M. Veendrick , Victor Zieren
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A voltage reference circuit and method for generating a reference voltage using the circuit uses a comparison of the voltages on first and second nodes of a diode resistor network to produce a comparison signal, which is then used to increase the voltage on an output of a charge pump to generate the reference voltage.
摘要翻译：使用该电路产生参考电压的电压参考电路和方法使用二极管电阻网络的第一和第二节点上的电压的比较来产生比较信号，然后将其用于增加电荷输出上的电压泵产生参考电压。

4. 发明授权

US07710136B2 Intergrated circuit self-test architecture 失效
标题翻译：集成电路自检架构
公开(公告)号：US07710136B2
公开(公告)日：2010-05-04
申请号：US11720317
申请日：2005-11-23
申请人： Marcel Pelgrom , Hendricus J M Veendrick
发明人： Marcel Pelgrom , Hendricus J M Veendrick
IPC分类号： G01R31/02
CPC分类号： G01R31/318536 , G01R31/3167
摘要： An integrated circuit (1) comprises a monitor (M1, M3, M3) operable to produce monitor data in dependence upon a measured parameter of the integrated circuit (1); and a self test controller (28) connected to receive monitor data from the monitor (M1, M2, M3). The self-test controller is also operable to output self test data from the integrated circuit. The monitor includes an output shift register (SR1, SR2, SR3) and is operable to output monitor data through the shift register (SR1, SR2, SR3). Such a system enables simplified communication of system self test results on an integrated circuit.
摘要翻译：集成电路（1）包括可根据集成电路（1）的测量参数产生监视数据的监视器（M1，M3，M3）。以及连接以从监视器（M1，M2，M3）接收监视数据的自检控制器（28）。自检控制器还可以从集成电路输出自检数据。监视器包括输出移位寄存器（SR1，SR2，SR3），并且可操作以通过移位寄存器（SR1，SR2，SR3）输出监视数据。这样的系统能够简化集成电路系统自检结果的通信。

5. 发明授权

US08139401B2 Integrated circuit with a memory matrix with a delay monitoring column 有权
标题翻译：具有带延迟监控列的存储器矩阵的集成电路
公开(公告)号：US08139401B2
公开(公告)日：2012-03-20
申请号：US12866876
申请日：2009-02-09
申请人： Hendricus J. M. Veendrick , Harold G. P. Benten , Agnese A. M. Bargagli-Stoffi , Patrick Van de Steeg
发明人： Hendricus J. M. Veendrick , Harold G. P. Benten , Agnese A. M. Bargagli-Stoffi , Patrick Van de Steeg
IPC分类号： G11C11/00 , G11C5/06 , G11C7/00
CPC分类号： H01L27/1104 , G11C11/41 , G11C11/413 , G11C29/50 , G11C29/50012 , H01L27/0207 , H01L27/105 , H01L27/11
摘要： An integrated circuit has a matrix of rows and columns of cells (10, 18, 19), each cell (10, 18, 19) comprising a first inverter (100) and a second inverter (102). First columns have a bit-line (12a,b), the first inverter (100) and the second inverter (102) in each cell of the first columns being cross-coupled to each other and coupled to bit-line (12a,b) of the associated first column. A further column is provided in the matrix with bit line fragments (16) that are mutually disconnected. Delays are monitored by coupling at least the first inverters (100) of cells in respective pairs of rows in series via the bit-line fragments and measuring a delay during signal propagation through the series connection, for example by incorporating the series of inverters in a ring oscillator.
摘要翻译：集成电路具有单元行（10,18,19）的行和列的矩阵，每个单元（10,18,19）包括第一反相器（100）和第二反相器（102）。第一列具有位线（12a，b），第一列的每个单元中的第一反相器（100）和第二反相器（102）彼此交叉耦合并耦合到位线（12a，b））相关联的第一列。在矩阵中提供另一列，其中相互断开的位线片段（16）。通过经由比特线片段串联耦合至少对应的成对行中的单元的第一反相器（100）来监测延迟，并且例如通过将串联的反相器并入到串联片段中来测量在信号传播期间的延迟环形振荡器。

6. 发明授权

US07928882B2 Monitoring physical operating parameters of an integrated circuit 有权
标题翻译：监控集成电路的物理操作参数
公开(公告)号：US07928882B2
公开(公告)日：2011-04-19
申请号：US11720190
申请日：2005-11-07
申请人： Hendricus J M Veendrick , Marcel Pelgrom , Violeta Petrescu
发明人： Hendricus J M Veendrick , Marcel Pelgrom , Violeta Petrescu
IPC分类号： H03M1/12 , H03M1/34
CPC分类号： G01R31/31723 , G01R31/317
摘要： An integrated circuit comprises a plurality of sensing circuits (12), each for detecting whether a respective physical operating parameter is above or below a respective reference value. The integrated circuit contains a serial shift register (11) for shifting digital data signals that represent the respective reference values from a successive approximation update circuit (14) to the sensing circuits (12) and back to the successive approximation update circuit (14). Detection results of the sensing circuits (12) are shifted to the successive approximation update circuit (14) with the digital data signals. The successive approximation update circuit (14) is used to form the digital data so that the reference values form successive approximations of the physical operating parameter values during an analog to digital conversion process. In this way the successive approximation update circuit (14) is shared by a plurality of sensing circuits (12).
摘要翻译：集成电路包括多个检测电路（12），每个检测电路用于检测相应的物理操作参数是否高于或低于相应的参考值。集成电路包含用于将表示来自逐次逼近更新电路（14）的各个参考值的数字数据信号移位到感测电路（12）并返回到逐次逼近更新电路（14）的串行移位寄存器（11）。感测电路（12）的检测结果用数字数据信号转移到逐次逼近更新电路（14）。逐次逼近更新电路（14）用于形成数字数据，使得参考值在模数转换过程期间形成物理操作参数值的逐次逼近。以这种方式，逐次逼近更新电路（14）由多个感测电路（12）共享。

7. 发明授权

US07616051B2 Integrated circuit, electronic device and integrated circuit control method 有权
标题翻译：集成电路，电子器件和集成电路控制方法
公开(公告)号：US07616051B2
公开(公告)日：2009-11-10
申请号：US11911881
申请日：2006-04-20
申请人： Hendricus J. M. Veendrick , Atul Katoch
发明人： Hendricus J. M. Veendrick , Atul Katoch
IPC分类号： G05F1/10 , H03K17/16
CPC分类号： H03K19/0019
摘要： An integrated circuit (10) comprises a plurality of functional blocks (101, 102, 103), each of the functional blocks (101, 102, 103) being coupled between a first power supply line (110) and a second power supply line (120). A first functional block (101) is coupled to the first power supply line (110) via a first conductive path including a first switch (131) and a second functional block (102) is coupled to the first power supply line (110) via a second conductive path including a second switch (132), the first switch (131) and the second switch (132) being arranged to respectively disconnect the first functional block (101) and the second functional block (102) from the first power supply line (110) for switching said functional blocks (101, 102) from an active mode to a standby mode. The IC (10) comprises a further switch (141) having a first terminal coupled to a node (121) of the first conductive path between the first switch (131) and the first functional block (101) and a second terminal coupled to a node (122) of the second conductive path between the second switch (132) and the second functional block (102). The further switch (141) has a control terminal responsive to an enable signal indicating that the first switch (131) and the second switch (132) are disabled, thus allowing the recycling of charge between the first functional block (101) and the second functional block (102).
摘要翻译：集成电路（10）包括多个功能块（101,102,103），每个功能块（101,102,103）被耦合在第一电源线（110）和第二电源线（ 120）。第一功能块（101）经由包括第一开关（131）的第一导电路径耦合到第一电源线（110），并且第二功能块（102）经由第一电源线（110）经由包括第二开关（132）的第二导电路径，所述第一开关（131）和所述第二开关（132）被布置成分别将所述第一功能块（101）和所述第二功能块（102）与所述第一电源线路（110），用于将所述功能块（101,102）从活动模式切换到待机模式。 IC（10）包括另外的开关（141），其具有耦合到第一开关（131）和第一功能块（101）之间的第一导电路径的节点（121）的第一端子和耦合到第一端子在第二开关（132）和第二功能块（102）之间的第二导电路径的节点（122）。另外的开关（141）具有响应于指示第一开关（131）和第二开关（132）被禁用的使能信号的控制端子，从而允许在第一功能块（101）和第二开关功能块（102）。

8. 发明授权

US6081149A Electronic circuit with a clock switch 失效
标题翻译：电子电路带时钟开关
公开(公告)号：US6081149A
公开(公告)日：2000-06-27
申请号：US211927
申请日：1998-12-15
申请人： Hendricus J. M. Veendrick
发明人： Hendricus J. M. Veendrick
IPC分类号： G06F1/04 , G06F1/08 , G06F1/10 , G06F1/32 , H04L7/00 , H03K1/04 , H03K3/00
CPC分类号： G06F1/08 , H04L7/0083
摘要： An electronic circuit comprises clocked functional circuits which receive a clock signal via a clock switch. The clock switch contains an enabled non-inverting driver which switches a connection between a power supply input and a clock output on and off under control of a clock signal only when the clock switch is enabled by an enable signal. The clock switch also contains a transmission switch coupled between a clock input and the clock output. The transmission switch is controlled from the enable input and makes a conductive connection between the clock input and the clock output only when the clock switch is enabled by the enable signal. As a result, transitions in the clock signal reach the functional circuits with less delay and power take-up needed to drive the clock signal is distributed so that there is less supply bounce.
摘要翻译：电子电路包括通过时钟开关接收时钟信号的时钟功能电路。时钟开关包含一个使能的同相驱动器，只有在通过使能信号使能时钟开关时，才能在时钟信号的控制下，在电源输入和时钟输出之间切换连接。时钟开关还包含耦合在时钟输入和时钟输出之间的传输开关。传输开关由使能输入控制，只有在使能信号使能时钟开关时，才能在时钟输入和时钟输出之间进行导通连接。结果，时钟信号中的转换到达功能电路，延迟较小并且驱动时钟信号所需的功率需求被分配，从而减少了电源反弹。

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