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1. 发明授权

US08788550B1 Structures for LUT-based arithmetic in PLDs 有权
标题翻译：在PLD中基于LUT的算术的结构
公开(公告)号：US08788550B1
公开(公告)日：2014-07-22
申请号：US12484010
申请日：2009-06-12
申请人： Ketan Padalia , David Cashman , David Lewis , Andy L. Lee , Jay Schleicher , Jinyong Yuan , Henry Kim
发明人： Ketan Padalia , David Cashman , David Lewis , Andy L. Lee , Jay Schleicher , Jinyong Yuan , Henry Kim
IPC分类号： G06F7/38
CPC分类号： G06F7/575 , H03K19/177 , H03K19/17728
摘要： A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.
摘要翻译：可编程逻辑器件（PLD）包括通过PLD路由架构连接的多个逻辑阵列块（LAB）。至少一个LAB包括可配置为在多个级中算术组合多个二进制输入信号的逻辑元件（LE）。 LE包括具有K个输入（“K-LUT”）的查找表（LUT）逻辑。 K-LUT被配置为在K-LUT逻辑单元的相应输入处输入二进制输入信号，并且在K-LUT逻辑单元的多个输出处提供指示至少两个二进制输入信号的算术组合的多级。输入线网络包括输入线路网络，输入线路可配置为从PLD路由架构接收代表二进制输入信号的输入信号，并将输入信号提供给K-LUT。输出线网络包括输出线网络，输出线路被配置为从K-LUT接收表示二进制结果信号的输出信号，并向PLD路由架构提供输出信号。所描述的LUT可以有效地执行算术，以及非算术函数。

2. 发明授权

US07671626B1 Versatile logic element and logic array block 失效
公开(公告)号：US07671626B1
公开(公告)日：2010-03-02
申请号：US12202053
申请日：2008-08-29
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/177
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

3. 发明申请

US20080102288A1 COMPOSITES CONTAINING CROSSLINKABLE THERMOPLASTIC AND TPV SHOW LAYER 失效
标题翻译：包含可交换热塑性和TPV显示层的复合材料
公开(公告)号：US20080102288A1
公开(公告)日：2008-05-01
申请号：US11967468
申请日：2007-12-31
申请人： Liggett Cothran , Henry Kim , Timothy Pauli
发明人： Liggett Cothran , Henry Kim , Timothy Pauli
IPC分类号： B28B3/20 , B32B9/04
CPC分类号： B32B25/08 , B29C47/0004 , B29C47/0023 , B29C47/003 , B29C47/0038 , B29C47/0052 , B29C47/026 , B29C47/06 , B29C47/065 , B29C47/128 , B29C47/56 , B29C63/044 , B29K2009/00 , B29K2009/06 , B29K2021/00 , B29K2023/06 , B29K2023/16 , B29K2105/24 , B29K2301/10 , B29K2995/0087 , B29L2031/26 , B29L2031/265 , B29L2031/30 , B32B25/14 , B32B27/32 , B32B2307/554 , B32B2307/746 , B32B2319/00 , B32B2323/04 , B32B2323/16 , B32B2383/00 , B60J10/16 , B60J10/17 , B60J10/265 , B60J10/80 , Y10S428/923 , Y10S428/926 , Y10T428/26 , Y10T428/266 , Y10T428/269 , Y10T428/31663 , Y10T428/31855 , Y10T428/31909
摘要： Methods for forming a composite for use as a vehicle weather strip and the products formed thereby are disclosed in which a main body member is formed from an elastomer polymer and an abrasion resistant decorative layer including a blend of a crosslinkable thermoplastic polyolefin and a thermoplastic vulcanizate is applied thereon. The crosslinkable thermoplastic polyolefin preferably includes a crosslinkable olefin homopolymer. The olefin homopolymer preferably contains grafted silane functional groups to allow the material to be crosslinked in the presence of moisture. The abrasion resistant decorative layer may be extruded or otherwise applied onto the main body either prior to or after the main body member is cured and either prior to or after the crosslinkable polyolefin of the abrasion resistant decorative layer is crosslinked. The material of the abrasion resistant decorative layer may be extruded into sheet form and laminated onto the main body member.
摘要翻译：公开了用于形成用作车辆防风条的复合材料和由此形成的产品的方法，其中主体构件由弹性体聚合物形成，并且包括可交联热塑性聚烯烃和热塑性硫化橡胶的共混物的耐磨装饰层是施加在其上。可交联热塑性聚烯烃优选包括可交联的烯烃均聚物。烯烃均聚物优选含有接枝硅烷官能团，以允许材料在水分存在下进行交联。耐磨装饰层可以在主体构件固化之前或之后被挤出或以其它方式施加到主体上，并且在耐磨装饰层的可交联聚烯烃交联之前或之后。耐磨装饰层的材料可以挤出成片状并层压在主体部件上。

4. 发明申请

US20070250647A1 COMMUNICATION TERMINAL USING ETHERNET INTERFACE 审中-公开
标题翻译：使用以太网接口的通信终端
公开(公告)号：US20070250647A1
公开(公告)日：2007-10-25
申请号：US11670808
申请日：2007-02-02
申请人： Kwang Chul Jeon , Gwan-Hee You , Henry Kim
发明人： Kwang Chul Jeon , Gwan-Hee You , Henry Kim
IPC分类号： G06F15/16
CPC分类号： H04L43/0817
摘要： A system and method for controlling and monitoring a wireless communication device. Communication between a communication manager and a wireless communication device is via Ethernet data, and communication between an Ethernet interface controller and a wireless communication module, both in the wireless communication device is via USB data.
摘要翻译：一种用于控制和监测无线通信设备的系统和方法。通信管理器和无线通信设备之间的通信是经由以太网数据，无线通信设备中的以太网接口控制器和无线通信模块之间的通信是经由USB数据。

5. 发明授权

US07218155B1 Techniques for controlling on-chip termination resistance using voltage range detection 有权
标题翻译：使用电压范围检测控制片上终端电阻的技术
公开(公告)号：US07218155B1
公开(公告)日：2007-05-15
申请号：US11040343
申请日：2005-01-20
申请人： Tzung-Chin Chang , Xiaobao Wang , Henry Kim , Chiakang Sung , Khai Q. Nguyen , Bonnie Wang , Jeffrey Tyhach , Gopinath Rangan
发明人： Tzung-Chin Chang , Xiaobao Wang , Henry Kim , Chiakang Sung , Khai Q. Nguyen , Bonnie Wang , Jeffrey Tyhach , Gopinath Rangan
IPC分类号： H03B1/00
CPC分类号： H03K19/0005
摘要： Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using a calibration circuit. The calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When voltage between the external resistor and the group of transistors is within a selected range, the calibration circuit causes the effective resistance of the transistors to match the resistance of the external resistor as closely as possible. The calibration circuit enables another set of transistors in the IO buffer so that the effective on resistance of the transistors in the IO buffer closely match the resistance of the external resistor.
摘要翻译：提供了使用校准电路控制输入或输出（IO）缓冲器中的片上终端电阻的技术。校准电路监视外部电阻和片上晶体管组之间的电压。当外部电阻和晶体管组之间的电压在选定范围内时，校准电路会使晶体管的有效电阻尽可能接近外部电阻的电阻。校准电路使得IO缓冲器中的另一组晶体管能够使得IO缓冲器中的晶体管的有效导通电阻与外部电阻器的电阻紧密匹配。

6. 发明授权

US07218133B2 Versatile logic element and logic array block 有权
公开(公告)号：US07218133B2
公开(公告)日：2007-05-15
申请号：US11050111
申请日：2005-02-02
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Timothy Betz
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Timothy Betz
IPC分类号： H03K19/003
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

7. 发明申请

US20050127944A1 Versatile logic element and logic array block 有权
公开(公告)号：US20050127944A1
公开(公告)日：2005-06-16
申请号：US11050111
申请日：2005-02-02
申请人： David Lewis , Paul Leventis , Andy Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David Lewis , Paul Leventis , Andy Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

8. 发明授权

US5147081A Flat pack desoldering tool 失效
标题翻译：平包拆焊工具
公开(公告)号：US5147081A
公开(公告)日：1992-09-15
申请号：US757020
申请日：1991-09-09
申请人： Henry Kim
发明人： Henry Kim
IPC分类号： B23K1/018 , H05K3/34 , H05K13/04
CPC分类号： B23K1/018 , H05K13/0491 , H05K3/3494 , H05K2203/087 , H05K3/3421
摘要： A specialized desoldering iron utilizes a blade which takes the form of a quadrilateral enclosure having a pair of heating elements mounted to two opposite walls of the enclosure. The enclosure is shaped and dimensioned to fit over a quad flat pack integrated circuit such that the lower edges of the walls of the enclosure come down onto the soldered leads of the integrated circuit. The two heating elements provide enough heat to simultaneously desolder all of the leads of a large quad flat pack, and the enclosure is open-topped so that the large heat sinks which are mounted atop IC's that consume a high level of power do not interfere with the desoldering process.
摘要翻译：一种专门的脱焊铁器采用采用四边形外壳形式的刀片，其具有安装在外壳的两个相对壁上的一对加热元件。外壳的形状和尺寸适合于四边形扁平封装集成电路，使得外壳的壁的下边缘下降到集成电路的焊接引线上。两个加热元件提供足够的热量同时拆卸大型四边形扁平封装的所有引线，并且外壳是开顶的，以便安装在消费高功率的IC上的大型散热器不会干扰拆焊过程。

9. 发明申请

US20150108727A1 RECREATIONAL BOARD RISER 审中-公开
标题翻译：娱乐板上升
公开(公告)号：US20150108727A1
公开(公告)日：2015-04-23
申请号：US14103185
申请日：2013-12-11
申请人： Henry Kim
发明人： Henry Kim
IPC分类号： A63C10/14
CPC分类号： A63C10/14 , A63C10/04 , A63C10/18 , A63C10/20 , A63C10/26
摘要： A riser for mounting to a rider-support surface of a recreational board and having a binder connected thereto comprises a first plate and a second plate selectively connectable to the first plate along a length of the first plate so as to define a connection location. A plurality of separate and interchangeable dampening members is connectable to each of the first plate and second plate. The plurality of dampening members is spaced along a portion of each first and second plate which is opposite the connection location of the first and second plates. The plurality of dampening members includes a first dampening member and a second dampening member, each having a differing hardness.
摘要翻译：用于安装到娱乐板的骑手支撑表面并具有连接到其上的绑定件的提升器包括第一板和第二板，所述第一板和第二板沿着第一板的长度可选择性地连接到第一板，以便限定连接位置。多个分离和可互换的阻尼构件可连接到第一板和第二板中的每一个。多个阻尼构件沿着与第一和第二板的连接位置相对的每个第一和第二板的一部分间隔开。多个阻尼构件包括第一阻尼构件和第二阻尼构件，每个具有不同的硬度。

10. 发明授权

US07590879B1 Clock edge de-skew 有权
标题翻译：时钟边缘去偏移
公开(公告)号：US07590879B1
公开(公告)日：2009-09-15
申请号：US11043524
申请日：2005-01-24
申请人： Henry Kim , Bonnie I. Wang , ChiaKang Sung , Joseph Huang
发明人： Henry Kim , Bonnie I. Wang , ChiaKang Sung , Joseph Huang
IPC分类号： G06F1/12 , G06F9/00 , G06F13/42
CPC分类号： G06F13/4243
摘要： Circuits, methods, and apparatus for deskewing rising and falling edges of a clock signal. One embodiment of the present invention utilizes a delay element in a data path to adjust a data signal such that a clock signal is centered relative to the data. A further embodiment of the present invention recovers a double-data rate signal using two flip-flops, one clocked by clock rising edges, the other clocked by clock falling edges. An additional delay element is inserted in front of one or both flip-flop clock inputs. If two additional delay elements are used, they are independently adjustable such that each edge can be independently adjusted for improved data recovery.
摘要翻译：用于对时钟信号的上升沿和下降沿进行偏移的电路，方法和装置。本发明的一个实施例利用数据路径中的延迟元件来调整数据信号，使得时钟信号相对于数据居中。本发明的另一实施例使用两个触发器来恢复双数据速率信号，其中一个触发器由时钟上升沿计时，另一个由时钟下降沿计时。在一个或两个触发器时钟输入的前面插入一个附加的延迟元件。如果使用两个额外的延迟元件，则它们可独立调节，以便可以独立调整每个边沿以改善数据恢复。

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