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1. 发明授权

US09594859B1 Apparatus and associated methods for parallelizing clustering and placement 有权
标题翻译：用于并行聚类和放置的装置和相关方法
公开(公告)号：US09594859B1
公开(公告)日：2017-03-14
申请号：US12040730
申请日：2008-02-29
申请人： Ketan Padalia , Adrian Ludwin , Ryan Fung , Vaughn Betz
发明人： Ketan Padalia , Adrian Ludwin , Ryan Fung , Vaughn Betz
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5036 , G06F9/46 , G06F17/10 , G06F17/504 , G06F17/505 , G06F17/5054 , G06F17/5072
摘要： A system for parallelizing software in computer-aided design (CAD) software for circuit design includes a computer. The computer is configured to form or optimize a plurality of clusters in parallel. Each cluster in the plurality of clusters includes a set of nodes in a netlist in a design. The computer is configured to determine placements for blocks in a netlist in parallel, based on iterative improvement, partitioning, or analytic techniques.
摘要翻译：用于电路设计的计算机辅助设计（CAD）软件中并行化软件的系统包括计算机。计算机被配置为并行地形成或优化多个簇。多个群集中的每个群集包括设计中网表中的一组节点。计算机被配置为基于迭代改进，分区或分析技术来并行地确定网表中的块的布局。

2. 发明授权

US08788550B1 Structures for LUT-based arithmetic in PLDs 有权
标题翻译：在PLD中基于LUT的算术的结构
公开(公告)号：US08788550B1
公开(公告)日：2014-07-22
申请号：US12484010
申请日：2009-06-12
申请人： Ketan Padalia , David Cashman , David Lewis , Andy L. Lee , Jay Schleicher , Jinyong Yuan , Henry Kim
发明人： Ketan Padalia , David Cashman , David Lewis , Andy L. Lee , Jay Schleicher , Jinyong Yuan , Henry Kim
IPC分类号： G06F7/38
CPC分类号： G06F7/575 , H03K19/177 , H03K19/17728
摘要： A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.
摘要翻译：可编程逻辑器件（PLD）包括通过PLD路由架构连接的多个逻辑阵列块（LAB）。至少一个LAB包括可配置为在多个级中算术组合多个二进制输入信号的逻辑元件（LE）。 LE包括具有K个输入（“K-LUT”）的查找表（LUT）逻辑。 K-LUT被配置为在K-LUT逻辑单元的相应输入处输入二进制输入信号，并且在K-LUT逻辑单元的多个输出处提供指示至少两个二进制输入信号的算术组合的多级。输入线网络包括输入线路网络，输入线路可配置为从PLD路由架构接收代表二进制输入信号的输入信号，并将输入信号提供给K-LUT。输出线网络包括输出线网络，输出线路被配置为从K-LUT接收表示二进制结果信号的输出信号，并向PLD路由架构提供输出信号。所描述的LUT可以有效地执行算术，以及非算术函数。

3. 发明申请

US20060225021A1 Automatic adjustment of optimization effort in configuring programmable devices 有权
标题翻译：自动调整配置可编程设备的优化工作
公开(公告)号：US20060225021A1
公开(公告)日：2006-10-05
申请号：US11097592
申请日：2005-04-01
申请人： Ketan Padalia , Jason Peters , Vaughn Betz
发明人： Ketan Padalia , Jason Peters , Vaughn Betz
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： User designs are assigned to a category for each design goal associated with the user design. Each category represents the difficulty of satisfying a design goal. Optimization phases are tailored to different combinations of categories and are selected according to the categories assigned to the user design. A ranking of the relative difficulty of the design goals is determined from the categories associated with the user design. Parameters of an optimization phase can be modified in accordance with this ranking to focus optimization efforts on specific design goals. The parameters may be weights of a cost function used by the optimization phase to evaluate alternative configurations of the user design. The user design can be re-classified into an additional category if the results of the optimization phase do not satisfy design goals, and additional optimization phases are selected based on this re-classification to further optimize the user design.
摘要翻译：用户设计被分配到与用户设计相关联的每个设计目标的类别。每个类别代表满足设计目标的难度。优化阶段根据类别的不同组合进行调整，并根据分配给用户设计的类别进行选择。根据与用户设计相关的类别确定设计目标相对难度的排名。优化阶段的参数可以根据这个排名进行修改，将优化工作集中在具体的设计目标上。参数可以是优化阶段用于评估用户设计的替代配置的成本函数的权重。如果优化阶段的结果不满足设计目标，则可以将用户设计重新分类为另外的类别，并且基于该重新分类来选择额外的优化阶段以进一步优化用户设计。

4. 发明授权

US08539418B1 Method and apparatus for performing efficient incremental compilation 有权
标题翻译：执行高效增量编译的方法和装置
公开(公告)号：US08539418B1
公开(公告)日：2013-09-17
申请号：US13600371
申请日：2012-08-31
申请人： Ketan Padalia , Ryan Fung
发明人： Ketan Padalia , Ryan Fung
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5022
摘要： A method for designing a system on a target device includes identifying candidate portions in the system to preserve based on similarities between the system and another system. Preservation criteria are applied on the candidate portions in the system to preserve to identify portions of the system to preserve. Design results from the another system are reused for portions in the system that are preserved.
摘要翻译：用于在目标设备上设计系统的方法包括基于系统与另一系统之间的相似性来识别系统中的候选部分。保存标准被应用于系统中的候选部分以保留以标识要保存的系统的部分。来自另一个系统的设计结果重新用于系统中保留的部分。

5. 发明授权

US07415682B2 Automatic adjustment of optimization effort in configuring programmable devices 有权
标题翻译：自动调整配置可编程设备的优化工作
公开(公告)号：US07415682B2
公开(公告)日：2008-08-19
申请号：US11097592
申请日：2005-04-01
申请人： Ketan Padalia , Jason Peters , Vaughn Betz
发明人： Ketan Padalia , Jason Peters , Vaughn Betz
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054
摘要： User designs are assigned to a category for each design goal associated with the user design. Each category represents the difficulty of satisfying a design goal. Optimization phases are tailored to different combinations of categories and are selected according to the categories assigned to the user design. A ranking of the relative difficulty of the design goals is determined from the categories associated with the user design. Parameters of an optimization phase can be modified in accordance with this ranking to focus optimization efforts on specific design goals. The parameters may be weights of a cost function used by the optimization phase to evaluate alternative configurations of the user design. The user design can be re-classified into an additional category if the results of the optimization phase do not satisfy design goals, and additional optimization phases are selected based on this re-classification to further optimize the user design.
摘要翻译：用户设计被分配到与用户设计相关联的每个设计目标的类别。每个类别代表满足设计目标的难度。优化阶段根据类别的不同组合进行调整，并根据分配给用户设计的类别进行选择。根据与用户设计相关的类别确定设计目标相对难度的排名。优化阶段的参数可以根据这个排名进行修改，将优化工作集中在具体的设计目标上。参数可以是优化阶段用于评估用户设计的替代配置的成本函数的权重。如果优化阶段的结果不满足设计目标，则可以将用户设计重新分类为另外的类别，并且基于该重新分类来选择额外的优化阶段以进一步优化用户设计。

6. 发明授权

US06871328B1 Method for mapping logic design memory into physical memory device of a programmable logic device 有权
标题翻译：将逻辑设计存储器映射到可编程逻辑器件的物理存储器件的方法
公开(公告)号：US06871328B1
公开(公告)日：2005-03-22
申请号：US10294836
申请日：2002-11-14
申请人： Ryan Fung , Ketan Padalia
发明人： Ryan Fung , Ketan Padalia
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method is provided for mapping logic design memory into physical memory devices of a programmable logic device. User constraints and physical constraints may be taken into account in generating the mapping solution. Functional block layout on the programmable logic device may be taken into account when generating the mapping solution. Multiple types of physical memory types may be considered and logic design memory may be mapped to those types of physical memory devices that are determined to be the most appropriate. A mapping solution may be optimized using, for example, simulated annealing.
摘要翻译：提供了一种用于将逻辑设计存储器映射到可编程逻辑器件的物理存储器件中的方法。在生成映射解决方案时可以考虑用户约束和物理约束。在生成映射解决方案时，可以考虑可编程逻辑器件上的功能块布局。可以考虑多种类型的物理存储器类型，并且可以将逻辑设计存储器映射到被确定为最合适的那些类型的物理存储器设备。可以使用例如模拟退火来优化映射解决方案。

7. 发明授权

US07707532B1 Techniques for grouping circuit elements into logic blocks 失效
标题翻译：将电路元件分组成逻辑块的技术
公开(公告)号：US07707532B1
公开(公告)日：2010-04-27
申请号：US11844216
申请日：2007-08-23
申请人： Ketan Padalia , Kimberly Bozman , Vaughn Betz
发明人： Ketan Padalia , Kimberly Bozman , Vaughn Betz
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/505 , G06F17/5072 , G06F17/5077 , Y02T10/82
摘要： Techniques are provided for grouping circuits in a user design for a programmable integrated circuit into logic blocks. A packing tool separates each circuit element into individual abstract blocks and groups the abstract block into logic blocks. A determination is made whether placement information indicates that a design goal would be improved by rearranging at least a portion of the user design. The user design can be rearranged by moving one or more of the abstract blocks into different logic blocks than the ones they were previously grouped with. Circuit elements in the same logic block can be separated and placed into different logic blocks to improve routability of the user design and signal timing.
摘要翻译：提供了用于将可编程集成电路的用户设计中的电路分组成逻辑块的技术。包装工具将每个电路元件分成单独的抽象块，并将抽象块分组成逻辑块。确定放置信息是否指示通过重新排列用户设计的至少一部分来提高设计目标。可以通过将抽象块中的一个或多个移动到与之前分组的逻辑块不同的逻辑块中来重新排列用户设计。相同逻辑块中的电路元件可以分离并放置到不同的逻辑块中，以改善用户设计和信号时序的可布线性。

8. 发明授权

US07681165B2 Apparatus and methods for congestion estimation and optimization for computer-aided design software 失效
标题翻译：计算机辅助设计软件拥塞估计和优化的装置和方法
公开(公告)号：US07681165B2
公开(公告)日：2010-03-16
申请号：US11467975
申请日：2006-08-29
申请人： Jason Peters , Ketan Padalia , Adrian Ludwin
发明人： Jason Peters , Ketan Padalia , Adrian Ludwin
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of performing placement of resources in a computer-aided design (CAD) tool includes performing a first congestion analysis, proposing a placement move, and evaluating the placement move. The method further includes incrementally updating information used for performing another congestion analysis.
摘要翻译：在计算机辅助设计（CAD）工具中执行资源放置的方法包括执行第一拥塞分析，提出放置移动以及评估放置移动。该方法还包括递增地更新用于执行另一个拥塞分析的信息。

9. 发明授权

US07370291B2 Method for mapping logic design memory into physical memory devices of a programmable logic device 有权
标题翻译：将逻辑设计存储器映射到可编程逻辑器件的物理存储器件的方法
公开(公告)号：US07370291B2
公开(公告)日：2008-05-06
申请号：US11069887
申请日：2005-02-28
申请人： Ryan Fung , Ketan Padalia
发明人： Ryan Fung , Ketan Padalia
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method is provided for mapping logic design memory into physical memory devices of a programmable logic device. User constraints and physical constraints may be taken into account in generating the mapping solution. Functional block layout on the programmable logic device may be taken into account when generating the mapping solution. Multiple types of physical memory types may be considered and logic design memory may be mapped to those types of physical memory devices that are determined to be the most appropriate. A mapping solution may be optimized using, for example, simulated annealing.
摘要翻译：提供了一种用于将逻辑设计存储器映射到可编程逻辑器件的物理存储器件中的方法。在生成映射解决方案时可以考虑用户约束和物理约束。在生成映射解决方案时，可以考虑可编程逻辑器件上的功能块布局。可以考虑多种类型的物理存储器类型，并且可以将逻辑设计存储器映射到被确定为最合适的那些类型的物理存储器设备。可以使用例如模拟退火来优化映射解决方案。

10. 发明授权

US07275228B1 Techniques for grouping circuit elements into logic blocks 有权
标题翻译：将电路元件分组成逻辑块的技术
公开(公告)号：US07275228B1
公开(公告)日：2007-09-25
申请号：US10716309
申请日：2003-11-17
申请人： Ketan Padalia , Kimberly Bozman , Vaughn Betz
发明人： Ketan Padalia , Kimberly Bozman , Vaughn Betz
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/505 , G06F17/5072 , G06F17/5077 , Y02T10/82
摘要： Techniques are provided for grouping circuits in a user design for a programmable integrated circuit into logic blocks. A packing tool separates each circuit element into individual abstract blocks and groups the abstract block into logic blocks. A determination is made whether placement information indicates that a design goal would be improved by rearranging at least a portion of the user design. The user design can be rearranged by moving one or more of the abstract blocks into different logic blocks than the ones they were previously grouped with. Circuit elements in the same logic block can be separated and placed into different logic blocks to improve routability of the user design and signal timing.
摘要翻译：提供了用于将可编程集成电路的用户设计中的电路分组成逻辑块的技术。包装工具将每个电路元件分成单独的抽象块，并将抽象块分组成逻辑块。确定放置信息是否指示通过重新排列用户设计的至少一部分来提高设计目标。可以通过将抽象块中的一个或多个移动到与之前分组的逻辑块不同的逻辑块中来重新排列用户设计。相同逻辑块中的电路元件可以分离并放置到不同的逻辑块中，以改善用户设计和信号时序的可布线性。

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