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1. 发明授权

US09111960B2 Semiconductor devices with vertical channel transistors 有权
标题翻译：具有垂直沟道晶体管的半导体器件
公开(公告)号：US09111960B2
公开(公告)日：2015-08-18
申请号：US13242660
申请日：2011-09-23
申请人： Hui-Jung Kim , Yongchul Oh , Daeik Kim , Hyun-Woo Chung
发明人： Hui-Jung Kim , Yongchul Oh , Daeik Kim , Hyun-Woo Chung
IPC分类号： H01L29/78 , H01L29/66 , H01L27/108
CPC分类号： H01L29/66666 , H01L27/10876 , H01L29/7827
摘要： Semiconductor devices with vertical channel transistors, the devices including semiconductor patterns disposed on a substrate, first gate patterns disposed between the semiconductor patterns on the substrate, a second gate pattern spaced apart from the first gate patterns by the semiconductor patterns, and conductive lines crossing the first gate patterns. The second gate pattern includes a first portion extending parallel to the first gate patterns and a second portion extending parallel to the conductive lines.
摘要翻译：具有垂直沟道晶体管的半导体器件，包括设置在衬底上的半导体图案的器件，设置在衬底上的半导体图案之间的第一栅极图案，通过半导体图案与第一栅极图案间隔开的第二栅极图案，第一门模式。第二栅极图案包括平行于第一栅极图案延伸的第一部分和平行于导电线延伸的第二部分。

2. 发明授权

US08552472B2 Integrated circuit devices including vertical channel transistors with shield lines interposed between bit lines and methods of fabricating the same 有权
标题翻译：集成电路器件，包括垂直沟道晶体管，屏蔽线插入位线之间，以及制造它们的方法
公开(公告)号：US08552472B2
公开(公告)日：2013-10-08
申请号：US13155688
申请日：2011-06-08
申请人： Hui-jung Kim , Yong-chul Oh , Yoo-sang Hwang , Hyun-woo Chung
发明人： Hui-jung Kim , Yong-chul Oh , Yoo-sang Hwang , Hyun-woo Chung
IPC分类号： H01L27/10 , H01L29/778 , H01L27/105
CPC分类号： H01L29/7788 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L29/7827
摘要： An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed.
摘要翻译：集成电路装置包括沿着第一方向从基板突出的多个支柱。每个支柱包括在其相对端的源极/漏极区域和在源极/漏极区域之间延伸的沟道区域。多个导电位线在基本上垂直于第一方向的第二方向上在基板上邻近柱子延伸。多个导电屏蔽线在第二方向上在基板上延伸，使得每个屏蔽线在相邻的位线之间延伸。还讨论了相关的制造方法。

3. 发明授权

US08447259B2 Mode-switching low-noise amplifier and wide-band RF receiver 有权
标题翻译：模式切换低噪声放大器和宽带射频接收器
公开(公告)号：US08447259B2
公开(公告)日：2013-05-21
申请号：US12358372
申请日：2009-01-23
申请人： Jae-Hong Chang , Hyung-Ki Ahn , Hui-Jung Kim
发明人： Jae-Hong Chang , Hyung-Ki Ahn , Hui-Jung Kim
IPC分类号： H03D11/02
CPC分类号： H04B1/18 , H03F3/45179
摘要： A mode-switching LNA generally includes an input unit, an output unit and a bias voltage generator. The input unit amplifies an input signal to generate an amplified signal. The output unit receives the amplified signal from the input unit and operates either in an oscillation mode or in an amplification mode in response to a control signal to generate an output signal having a center frequency equal to a target frequency. The control signal indicates whether the center frequency of the output signal is the same as the target frequency. The bias voltage generator provides an input bias voltage to the input unit in response to the control signal, where the input bias voltage includes a first bias voltage in the amplification mode and a second bias voltage in the oscillation mode.
摘要翻译：模式切换LNA一般包括输入单元，输出单元和偏置电压发生器。输入单元放大输入信号以产生放大信号。输出单元从输入单元接收放大的信号，并响应于控制信号以振荡模式或放大模式操作，以产生具有等于目标频率的中心频率的输出信号。控制信号表示输出信号的中心频率是否与目标频率相同。偏置电压发生器响应于控制信号向输入单元提供输入偏置电压，其中输入偏置电压包括放大模式中的第一偏置电压和振荡模式中的第二偏置电压。

4. 发明授权

US08294131B2 Integrated circuit devices including low-resistivity conductive patterns in recessed regions 有权
标题翻译：集成电路器件包括凹陷区域中的低电阻率导电图案
公开(公告)号：US08294131B2
公开(公告)日：2012-10-23
申请号：US12826896
申请日：2010-06-30
申请人： Kang-Uk Kim , Yongchul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim
发明人： Kang-Uk Kim , Yongchul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim
IPC分类号： H01L29/02
CPC分类号： H01L27/228 , H01L27/0207 , H01L27/10876 , H01L27/10885 , H01L27/2454 , H01L27/2463
摘要： An integrated circuit device includes a device isolation pattern on a semiconductor substrate to define an active area therein. The active area includes a doped region therein. A conductive pattern extends on the active area and electrically contacts the doped region. The conductive pattern has a lower resistivity than the doped region. The conductive pattern may be disposed in a recessed region having a bottom surface lower than a top surface of the active area. A channel pillar electrically contacts to the doped region and extends therefrom in a direction away from the substrate. A conductive gate electrode is disposed on a sidewall of the channel pillar, and a gate dielectric layer is disposed between the gate electrode and the sidewall of the channel pillar.
摘要翻译：集成电路器件包括在半导体衬底上的器件隔离图案，以在其中限定有效区域。有源区域包括其中的掺杂区域。导电图案在有源区上延伸并与掺杂区电接触。导电图案具有比掺杂区域更低的电阻率。导电图案可以设置在具有低于有源区域的顶表面的底表面的凹陷区域中。通道柱与掺杂区电接触并从远离衬底的方向从其延伸。导电栅电极设置在通道柱的侧壁上，并且栅极电介质层设置在沟道柱的栅电极和侧壁之间。

5. 发明申请

US20110303974A1 INTEGRATED CIRCUIT DEVICES INCLUDING VERTICAL CHANNEL TRANSISTORS WITH SHIELD LINES INTERPOSED BETWEEN BIT LINES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：集成电路设备，包括垂直通道晶体管与位线之间插入的屏蔽线及其制造方法
公开(公告)号：US20110303974A1
公开(公告)日：2011-12-15
申请号：US13155688
申请日：2011-06-08
申请人： Hui-jung Kim , Yong-chul Oh , Yoo-sang Hwang , Hyun-woo Chung
发明人： Hui-jung Kim , Yong-chul Oh , Yoo-sang Hwang , Hyun-woo Chung
IPC分类号： H01L29/78
CPC分类号： H01L29/7788 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L29/7827
摘要： An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed.
摘要翻译：集成电路装置包括沿着第一方向从基板突出的多个支柱。每个支柱包括在其相对端的源极/漏极区域和在源极/漏极区域之间延伸的沟道区域。多个导电位线在基本上垂直于第一方向的第二方向上在基板上邻近柱子延伸。多个导电屏蔽线在第二方向上在基板上延伸，使得每个屏蔽线在相邻的位线之间延伸。还讨论了相关的制造方法。

6. 发明申请

US20090242975A1 Vertical pillar transistor 有权
标题翻译：立柱晶体管
公开(公告)号：US20090242975A1
公开(公告)日：2009-10-01
申请号：US12382898
申请日：2009-03-26
申请人： Hui-Jung Kim , Yong-Chul Oh , Jae-Man Yoon , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Hui-Jung Kim , Yong-Chul Oh , Jae-Man Yoon , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/10882 , H01L21/76232 , H01L21/823481 , H01L21/823487 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： A vertical pillar transistor may include a plurality of lower pillars, a plurality of upper pillars, a first insulation part, a second insulation part and a word line. The plurality of lower pillars protrudes substantially perpendicular to a substrate and is defined by a plurality of trenches. The plurality of lower pillars extends along a second direction and may be separated from each other along a first direction substantially perpendicular to the second direction. The plurality of upper pillars may be formed on the plurality of lower pillars. The plurality of upper pillars has a width substantially smaller than that of the plurality of lower pillars. The first insulation part has a substantially uniform thickness on a sidewall of each of the plurality of lower pillars. The second insulation part may be formed on the first insulation part to fill a gap between the adjacent upper pillars. The word line may be formed on the second insulation part and may extend between facing sidewalls of the adjacent pair of upper pillars along the first direction.
摘要翻译：垂直柱状晶体管可以包括多个下部支柱，多个上部支柱，第一绝缘部分，第二绝缘部分和字线。多个下支柱基本上垂直于基板突出并且由多个沟槽限定。多个下柱沿着第二方向延伸并且可以沿着基本上垂直于第二方向的第一方向彼此分离。多个上柱可以形成在多个下支柱上。多个上支柱具有比多个下支柱的宽度更小的宽度。第一绝缘部件在多个下支柱中的每一个的侧壁上具有基本均匀的厚度。第二绝缘部件可以形成在第一绝缘部分上以填充相邻的上部支柱之间的间隙。字线可以形成在第二绝缘部分上，并且可以沿着第一方向在相邻的一对上柱的相对侧壁之间延伸。

7. 发明申请

US20080173937A1 SEMICONDUCTOR MEMORY DEVICES INCLUDING VERTICALLY ORIENTED TRANSISTORS AND METHODS OF MANUFACTURING SUCH DEVICES 审中-公开
标题翻译：包括垂直方向的晶体管的半导体存储器件及其制造方法
公开(公告)号：US20080173937A1
公开(公告)日：2008-07-24
申请号：US12013069
申请日：2008-01-11
申请人： Hyun-Woo Chung , Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim
发明人： Hyun-Woo Chung , Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78642 , H01L21/823487 , H01L29/0657 , H01L29/4236 , H01L29/42392 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes a first active pattern including an upper portion and a lower portion formed on a substrate, a second active pattern formed on the first active pattern, and a gate surrounding the second active pattern. The upper portion of the first active pattern has a cross-sectional area substantially larger than that of the lower portion of the first active pattern. The first active pattern has a curved sidewall or a level sidewall. The second active pattern has a pillar structure. The gate provides a channel through the second active pattern.
摘要翻译：半导体器件包括第一有源图案，其包括形成在基板上的上部和下部，形成在第一有源图案上的第二有源图案和围绕第二有源图案的栅极。第一有源图案的上部具有基本上大于第一有源图案的下部的横截面积的横截面积。第一活动图案具有弯曲的侧壁或水平侧壁。第二活动图案具有支柱结构。门通过第二活动模式提供通道。

8. 发明申请

US20070298599A1 Method for fabricating multiple FETs of different types 有权
标题翻译：制造不同类型多个FET的方法
公开(公告)号：US20070298599A1
公开(公告)日：2007-12-27
申请号：US11804875
申请日：2007-05-21
申请人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Keun-Nam Kim , Hyun-Ju Sung , Hui-Jung Kim , Kyoung-Ho Jung
发明人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Keun-Nam Kim , Hyun-Ju Sung , Hui-Jung Kim , Kyoung-Ho Jung
IPC分类号： H01L21/8232
CPC分类号： H01L21/823412
摘要： For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.
摘要翻译：为了制造多个场效应晶体管（FET），第一导电层沉积在半导体衬底的第一和第二有源区上。在第二有源区上形成第一导电层以形成模具结构。在模具结构之间形成掩模结构。使用掩模结构或使用形成在模具结构的侧壁处的间隔来形成第二有源区，以形成翅片型场效应晶体管的多个鳍。在第一有源区上图案化第一导电层以形成不同类型的另一场效应晶体管的栅极。

9. 发明授权

US08304824B2 Semiconductor device comprising buried word lines 有权
标题翻译：包括掩埋字线的半导体器件
公开(公告)号：US08304824B2
公开(公告)日：2012-11-06
申请号：US12719493
申请日：2010-03-08
申请人： Hui-Jung Kim , Yong-Chul Oh , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Hui-Jung Kim , Yong-Chul Oh , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10891 , H01L27/0207 , H01L27/10817 , H01L27/10885 , H01L29/4236
摘要： A semiconductor device includes: an isolation layer for defining a plurality of active areas of a substrate, where the isolation layer is disposed on the substrate; a plurality of buried word lines having upper surfaces that are lower than the upper surfaces of the active areas, being surrounded by the active areas, and extending in a first direction parallel to a main surface of the substrate; a gate dielectric film interposed between the buried word lines and the active areas; and a plurality of buried bit lines having upper surfaces that are lower than the upper surfaces of the plurality of buried word lines and extending parallel to the main surface of the substrate in a second direction that differs from the first direction.
摘要翻译：半导体器件包括：用于限定衬底的多个有源区的隔离层，其中隔离层设置在衬底上; 具有比有源区域的上表面低的上表面的多个掩埋字线被有源区域包围，并且沿与基板的主表面平行的第一方向延伸; 介于掩埋字线和有源区之间的栅介质膜; 以及多个掩埋位线，其具有比所述多个掩埋字线的上表面低的上表面，并且在与所述第一方向不同的第二方向上平行于所述基板的主表面延伸。

10. 发明申请

US20120153379A1 SEMICONDUCTOR DEVICES WITH VERTICAL CHANNEL TRANSISTORS 有权
标题翻译：具有垂直通道晶体管的半导体器件
公开(公告)号：US20120153379A1
公开(公告)日：2012-06-21
申请号：US13242660
申请日：2011-09-23
申请人： Hui-Jung Kim , Yongchul Oh , Daeik Kim , Hyun-Woo Chung
发明人： Hui-Jung Kim , Yongchul Oh , Daeik Kim , Hyun-Woo Chung
IPC分类号： H01L29/78
CPC分类号： H01L29/66666 , H01L27/10876 , H01L29/7827
摘要： Semiconductor devices with vertical channel transistors, the devices including semiconductor patterns disposed on a substrate, first gate patterns disposed between the semiconductor patterns on the substrate, a second gate pattern spaced apart from the first gate patterns by the semiconductor patterns, and conductive lines crossing the first gate patterns. The second gate pattern includes a first portion extending parallel to the first gate patterns and a second portion extending parallel to the conductive lines.
摘要翻译：具有垂直沟道晶体管的半导体器件，包括设置在衬底上的半导体图案的器件，设置在衬底上的半导体图案之间的第一栅极图案，通过半导体图案与第一栅极图案间隔开的第二栅极图案，第一门模式。第二栅极图案包括平行于第一栅极图案延伸的第一部分和平行于导电线延伸的第二部分。

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