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1. 发明授权

US08933523B2 Single-chip referenced full-bridge magnetic field sensor 有权
标题翻译：单芯片参考全桥磁场传感器
公开(公告)号：US08933523B2
公开(公告)日：2015-01-13
申请号：US14112928
申请日：2012-04-06
申请人： James G. Deak , Insik Jin , Weifeng Shen , Songsheng Xue , Xiaofeng Lei
发明人： James G. Deak , Insik Jin , Weifeng Shen , Songsheng Xue , Xiaofeng Lei
IPC分类号： H01L27/22 , H01L43/02 , G01R33/09
CPC分类号： H01L43/02 , G01R33/098
摘要： The present invention discloses a single-chip referenced full-bridge magnetoresistive magnetic-field sensor. The single-chip sensor is a Wheatstone bridge arrangement of magnetoresistive sensing elements and reference elements. The sensing elements and reference elements are formed from either magnetic tunnel junctions or giant magnetoresistive materials. The sensitivity of the reference and sensor elements is controlled through one or a combination of magnetic bias, exchange bias, shielding, or shape anisotropy. Moreover, the bridge output is tuned by setting the ratio of the reference and sensor arm resistance values to a predetermined ratio that optimizes the bridge output for offset and symmetry. The single-chip referenced-bridge magnetic field sensor of the present invention exhibits excellent temperature stability, low offset voltage, and excellent voltage symmetry.
摘要翻译：本发明公开了一种单芯片参考全桥磁阻磁场传感器。单芯片传感器是一种惠斯通电桥布置的磁阻感应元件和参考元件。感测元件和参考元件由磁隧道结或巨磁阻材料形成。通过磁偏置，交换偏压，屏蔽或形状各向异性的一种或组合来控制参考和传感器元件的灵敏度。此外，通过将参考和传感器臂电阻值的比率设置为优化桥接输出的偏移和对称性的预定比率来调节桥输出。本发明的单芯片参考桥磁场传感器表现出优异的温度稳定性，低失调电压和优异的电压对称性。

2. 发明申请

US20140035570A1 SINGLE-CHIP PUSH-PULL BRIDGE-TYPE MAGNETIC FIELD SENSOR 有权
标题翻译：单片推拉式桥式磁场传感器
公开(公告)号：US20140035570A1
公开(公告)日：2014-02-06
申请号：US14009912
申请日：2012-04-01
申请人： Insik Jin , Xiaofeng Lei , James Geza Deak , Weifeng Shen , Songsheng Xue , Wei Li
发明人： Insik Jin , Xiaofeng Lei , James Geza Deak , Weifeng Shen , Songsheng Xue , Wei Li
IPC分类号： G01R33/09
CPC分类号： G01R33/09 , G01D5/145 , G01R33/0005 , G01R33/0011 , G01R33/098 , G06Q10/00 , G06Q2220/00 , G07F1/00 , H01L27/22 , H01L43/08
摘要： The present invention discloses a design of a single-chip push-pull bridge sensor, composed of magnetoresistive elements, utilizing on-chip permanent magnets. The permanent magnets are oriented to preset magnetization directions of free layers of adjacent sensor bridge arms so that they point to different directions with respect the same sensing direction, enabling push-pull operation. The push-pull bridge sensor of the present invention is integrated on a single chip. Additionally, an on-chip coil is disclosed to reset or calibrate the magnetization directions of the free layers of the magnetoresistive elements.
摘要翻译：本发明公开了利用片上永磁体的由磁阻元件构成的单片推挽桥式传感器的设计。永磁体被定向成相邻传感器桥臂的自由层的预定磁化方向，使得它们相对于相同感测方向指向不同的方向，从而能够进行推挽操作。本发明的推挽桥式传感器集成在单个芯片上。此外，公开了片上线圈以复位或校准磁阻元件的自由层的磁化方向。

3. 发明申请

US20140021571A1 Single-chip bridge-type magnetic field sensor and preparation method thereof 有权
标题翻译：单片桥式磁场传感器及其制备方法
公开(公告)号：US20140021571A1
公开(公告)日：2014-01-23
申请号：US14009834
申请日：2012-04-01
申请人： Xiaofeng Lei , Insik Jin , James Deak , Weifeng Geza Shen , Mingfeng Liu , Songsheng Xue
发明人： Xiaofeng Lei , Insik Jin , James Deak , Weifeng Geza Shen , Mingfeng Liu , Songsheng Xue
IPC分类号： H01L43/02
CPC分类号： H01L43/12 , B82Y10/00 , G01B7/30 , G01R33/0052 , G01R33/093 , G01R33/098 , G11B5/3909 , G11B5/3993 , G11B2005/3996 , H01L43/02 , H01L43/08
摘要： The present invention discloses a design and manufacturing method for a single-chip magnetic sensor bridge. The sensor bridge comprises four magnetoresistive elements. The magnetization of the pinned layer of each of the four magnetoresistive elements is set in the same direction, but the magnetization directions of the free layers of the magnetoresistive elements on adjacent arms of the bridge are set at different angles with respect to the pinned layer magnetization direction. The absolute values of the angles of the magnetization directions of the free layers of all four magnetoresistive elements are the same with respect with their pinning layers. The disclosed magnetic biasing scheme enables the integration of a push-pull Wheatstone bridge magnetic field sensor on a single chip with better performance, lower cost, and easier manufacturability than conventional magnetoresistive sensor designs.
摘要翻译：本发明公开了一种单芯片磁传感器桥的设计和制造方法。传感器桥包括四个磁阻元件。四个磁阻元件中的每一个的钉扎层的磁化被设定在相同的方向上，但是桥的相邻臂上的磁阻元件的自由层的磁化方向相对于被钉扎层磁化被设定在不同的角度方向。所有四个磁阻元件的自由层的磁化方向的角度的绝对值与它们的钉扎层相同。所公开的磁偏置方案使得能够将单个芯片上的推挽惠斯通电桥磁场传感器与传统的磁阻传感器设计相比具有更好的性能，更低的成本和更易于制造的能力。

4. 发明申请

US20130271125A1 Isolated Voltage Transducer 有权
标题翻译：隔离式电压传感器
公开(公告)号：US20130271125A1
公开(公告)日：2013-10-17
申请号：US13882111
申请日：2011-10-26
申请人： James G. Deak , Insik Jin , Xiaofeng Lei , Weifeng Shen , Songsheng Xue
发明人： James G. Deak , Insik Jin , Xiaofeng Lei , Weifeng Shen , Songsheng Xue
IPC分类号： G01R33/09
CPC分类号： G01R33/09 , G01R15/148 , G01R15/205 , G01R31/025 , G01R33/0017 , G01R33/091 , G01R33/098
摘要： A transducer is disclosed for detecting the AC and DC voltage difference between two nodes in an electrical circuit and electronically transmitting the measured voltage difference to an electrical system that is electrically isolated from the common mode potential of the two nodes. The voltage drop between two points in a circuit under test is determined by detecting the current flowing through a resistive shunt coil connected in parallel to the test points. Current through the resistive shunt coil is linearly proportional to the voltage difference between the test points, and it is detected by using a magnetic sensor that is separated from the shunt coil by an insulating dielectric barrier. The transducer can be packaged in a standard integrated circuit package in order to provide a small and low cost voltage transducer for test, measurement, control, and signal-isolation applications.
摘要翻译：公开了一种用于检测电路中的两个节点之间的AC和DC电压差的换能器，并将所测量的电压差电传送到与两个节点的共模电位电隔离的电气系统。通过检测流过与测试点并联连接的电阻分流线圈的电流来确定被测电路中两点之间的电压降。通过电阻分流线圈的电流与测试点之间的电压差成线性比例，并且通过使用通过绝缘电介质阻挡层与分流线圈分离的磁传感器来检测电流。传感器可以封装在标准集成电路封装中，以便为测试，测量，控制和信号隔离应用提供一个小型和低成本的电压传感器。

5. 发明授权

US08519495B2 Single line MRAM 失效
标题翻译：单线MRAM
公开(公告)号：US08519495B2
公开(公告)日：2013-08-27
申请号：US12372025
申请日：2009-02-17
申请人： Insik Jin , Hongyue Liu , Yong Lu , Xiaobin Wang
发明人： Insik Jin , Hongyue Liu , Yong Lu , Xiaobin Wang
IPC分类号： H01L29/82
CPC分类号： H01L43/08 , G11C11/1673 , G11C11/1675 , H01L27/228
摘要： A magnetic memory device includes a first electrode separated from a second electrode by a magnetic tunnel junction. The first electrode provides a write current path along a length of the first electrode. The magnetic tunnel junction includes a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation. The free magnetic layer is spaced from the first electrode a distance of less than 10 nanometers. A current passing along the write current path generates a magnetic field. The magnetic field switches the free magnetic layer magnetization orientation between a high resistance state magnetization orientation and a low resistance state magnetization orientation.
摘要翻译：磁存储器件包括通过磁性隧道结从第二电极分离的第一电极。第一电极沿着第一电极的长度提供写入电流路径。磁性隧道结包括具有可在高电阻状态磁化取向和低电阻状态磁化取向之间切换的磁化取向的自由磁性层。自由磁性层与第一电极间隔小于10纳米的距离。沿着写入电流路径的电流产生磁场。磁场在高电阻状态磁化取向和低电阻状态磁化取向之间切换自由磁层磁化取向。

6. 发明授权

US08367464B2 Nano-dimensional non-volatile memory cells 有权
标题翻译：纳米级非易失性存储单元
公开(公告)号：US08367464B2
公开(公告)日：2013-02-05
申请号：US13209809
申请日：2011-08-15
申请人： Venugopalan Vaithyanathan , Wei Tian , Insik Jin
发明人： Venugopalan Vaithyanathan , Wei Tian , Insik Jin
IPC分类号： H01L21/00
CPC分类号： H01L45/1233 , H01L27/2463 , H01L27/2472 , H01L45/085 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1641 , H01L45/1675
摘要： A non-volatile memory cell that includes a first electrode; a second electrode; and an electrical contact region that electrically connects the first electrode and the second electrode, the electrical contact region has a end portion and a continuous side portion, and together, the end portion and the continuous side portion form an open cavity, wherein the memory cell has a high resistance state and a low resistance state that can be switched by applying a voltage across the first electrode and the second electrode.
摘要翻译：一种包括第一电极的非易失性存储单元; 第二电极; 以及电接触区域，其电连接所述第一电极和所述第二电极，所述电接触区域具有端部和连续侧部，并且所述端部和所述连续侧部一起形成开放空腔，其中所述存储单元具有可以通过在第一电极和第二电极两端施加电压来切换的高电阻状态和低电阻状态。

7. 发明申请

US20120153400A1 TUNNELING TRANSISTORS 有权
标题翻译：隧道晶体管
公开(公告)号：US20120153400A1
公开(公告)日：2012-06-21
申请号：US12971393
申请日：2010-12-17
申请人： Insik Jin , Wei Tian , Venugopalan Vaithyanathan , Cedric Bedoya , Markus Siegert
发明人： Insik Jin , Wei Tian , Venugopalan Vaithyanathan , Cedric Bedoya , Markus Siegert
IPC分类号： H01L27/11 , H01L29/78
CPC分类号： H01L27/115 , B82Y10/00 , H01L29/66977
摘要： A transistor including a source; a drain; a gate region, the gate region including a gate; an island; and a gate oxide, wherein the gate oxide is positioned between the gate and the island; and the gate and island are coactively coupled to each other; and a source barrier and a drain barrier, wherein the source barrier separates the source from the gate region and the drain barrier separates the drain from the gate region.
摘要翻译：一种晶体管，包括一个源极; 排水栅极区域，所述栅极区域包括栅极; 一个岛屿; 和栅极氧化物，其中所述栅极氧化物位于所述栅极和岛之间; 门和岛彼此共同耦合; 源极屏障和漏极阻挡层，其中源极栅极将源极与栅极区域隔离，并且漏极栅极将漏极与栅极区域分离。

8. 发明授权

US08203894B2 Current cancellation for non-volatile memory 有权
标题翻译：当前取消非易失性存储器
公开(公告)号：US08203894B2
公开(公告)日：2012-06-19
申请号：US13081170
申请日：2011-04-06
申请人： Chulmin Jung , Insik Jin , YoungPil Kim , Yong Lu , Harry Hongyue Liu , Andrew John Carter
发明人： Chulmin Jung , Insik Jin , YoungPil Kim , Yong Lu , Harry Hongyue Liu , Andrew John Carter
IPC分类号： G11C7/22
CPC分类号： G11C11/1673
摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.
摘要翻译：一种用于从非易失性存储单元读取数据的方法和装置。在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列，每个行和列都由线驱动器控制。提供读取电路，其能够通过将非积分的第一参考值与非积分的第二参考值进行微分来读取预定存储器单元的逻辑状态。此外，在配置与预定存储单元相对应的列之后立即测量每个参考值以产生第一和第二电流量。

9. 发明申请

US20120149183A1 SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME 有权
标题翻译：肖特基二极管开关和包含该开关的记忆单元
公开(公告)号：US20120149183A1
公开(公告)日：2012-06-14
申请号：US13400364
申请日：2012-02-20
申请人： Young Pil Kim , Nurul Amin , Dadi Setiadi , Venugopalan Vaithyanathan , Wei Tian , Insik Jin
发明人： Young Pil Kim , Nurul Amin , Dadi Setiadi , Venugopalan Vaithyanathan , Wei Tian , Insik Jin
IPC分类号： H01L21/329
CPC分类号： H01L27/0814 , G11C11/161 , G11C11/1659 , G11C13/0002 , H01L21/84 , H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/11507 , H01L27/1203 , H01L27/224 , H01L27/2409 , H01L29/66143 , H01L29/66212 , H01L29/872 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/143 , H01L45/146 , H01L45/147
摘要： A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.
摘要翻译：一种开关元件，包括第一半导体层，所述第一半导体层具有第一部分和第二部分; 第二半导体层，所述第二半导体层具有第一部分和第二部分; 设置在所述第一半导体层和所述第二半导体层之间的绝缘层; 与所述第一半导体层的所述第一部分接触的第一金属接触形成第一结，并与所述第二半导体层的所述第一部分接触形成第二结; 第二金属触点与第一半导体层的第二部分接触形成第三结，并与第二半导体层的第二部分接触形成第四结，其中第一结和第四结是肖特基接触，第二结和第三结是欧姆接触。

10. 发明授权

US08124952B2 Programmable resistive memory cell with filament placement structure 有权
公开(公告)号：US08124952B2
公开(公告)日：2012-02-28
申请号：US13014935
申请日：2011-01-27
申请人： Insik Jin , Christina Hutchinson , Richard Larson , Lance Stover , Jaewoo Nam , Andrew Habermas
发明人： Insik Jin , Christina Hutchinson , Richard Larson , Lance Stover , Jaewoo Nam , Andrew Habermas
IPC分类号： H01L47/00
CPC分类号： G11C13/0011 , H01L21/0337 , H01L27/2463 , H01L45/085 , H01L45/1273 , H01L45/1675
摘要： Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has a filament placement structure thereon extending into the ion conductor material toward the first filament placement structure. The filament placement structure may have a height of at least about 2 nm.

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