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1. 发明授权

US10385391B2 Entangled mate sequencing 有权
公开(公告)号：US10385391B2
公开(公告)日：2019-08-20
申请号：US13497069
申请日：2010-09-22
申请人： Frederick P. Roth , Joseph C. Mellor , Yong Lu , Mark Chee
发明人： Frederick P. Roth , Joseph C. Mellor , Yong Lu , Mark Chee
IPC分类号： C40B20/00 , C12Q1/68 , C12Q1/6874
摘要： Methods and compositions are provided for performing a set of N DNA sequencing reaction cycles whereby sequence information is obtained for approximately 2*N nucleotide bases.

2. 发明授权

US09720433B2 Cellular power supply network, intelligent gateway and power supply control method thereof 有权
公开(公告)号：US09720433B2
公开(公告)日：2017-08-01
申请号：US13995884
申请日：2011-10-25
申请人： Yong Lu
发明人： Yong Lu
IPC分类号： G05F3/02 , H02H7/04 , H02J3/00 , H02J3/06 , H02J3/38
CPC分类号： G05F3/02 , H02H7/04 , H02J3/006 , H02J3/06 , H02J3/38 , Y04S10/20 , Y04S20/14
摘要： The embodiments of the present invention provide a cellular power supply network, an intelligent gateway and a power supply control method thereof. The cellular power supply network further comprises: at least one cellular power supply layer formed by a plurality of transformers connected as a cellular structure. In the embodiments of the present invention, the electricity energy can be transferred from one transformer to another transformer demanding power as needed, so that the power is more reasonably distributed and the energy utilization rate is improved. In the technical solutions of the present invention, when a certain transformer cannot work normally due to a fault, the electricity energy outside the transformer can be introduced into the user of the transformer using the cellular power supply network, so as to keep continuous power usage. Meanwhile, the transformer can be separated from the power supply network for repairing and maintenance.

3. 发明申请

US20140142251A1 FILLED ELASTOMER COMPRISING POLYURETHANE 审中-公开
标题翻译：填充弹性体包含聚氨酯
公开(公告)号：US20140142251A1
公开(公告)日：2014-05-22
申请号：US14131152
申请日：2012-07-04
申请人： Dong Liang , Weihua Ye , Yong Lu , Zhen Tong , Zhaohui Chen
发明人： Dong Liang , Weihua Ye , Yong Lu , Zhen Tong , Zhaohui Chen
IPC分类号： C08L9/06
摘要： The present invention relates to a method for producing a filled elastomer wherein a rubber composition is produced by mixing I) raw rubber, II) cross linking agent, III) filler, IV) isocyanate terminated polymer composition and optionally V) further additives and cross linking of the rubber composition. The present invention further relates to a filled elastomer obtainable according to said method and the use of filled elastomers according to the invention as shoe sole.
摘要翻译：本发明涉及一种填充弹性体的制造方法，其中通过混合I）生橡胶，II）交联剂，III）填料，IV）异氰酸酯封端的聚合物组合物和任选的V）进一步添加和交联来制备橡胶组合物的橡胶组合物。本发明还涉及根据所述方法可获得的填充弹性体和根据本发明的填充弹性体作为鞋底的用途。

4. 发明申请

US20140071731A1 One-Time Programmable Memory Cell 有权
标题翻译：一次性可编程存储单元
公开(公告)号：US20140071731A1
公开(公告)日：2014-03-13
申请号：US13608595
申请日：2012-09-10
申请人： Jonathan Schmitt , Roy Milton Carlson , Yong Lu , Owen Hynes
发明人： Jonathan Schmitt , Roy Milton Carlson , Yong Lu , Owen Hynes
IPC分类号： G11C17/12 , H01L27/088
CPC分类号： H01L23/5252 , H01L27/0629 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： A programmable memory cell including a thick oxide spacer transistor, a programmable thin oxide anti-fuse disposed adjacent to the thick oxide spacer transistor, and first and second thick oxide access transistors. The thick oxide spacer transistor and first and second thick oxide access transistors can include an oxide layer that is thicker than an oxide layer of the programmable thin oxide anti-fuse. The programmable thin oxide anti-fuse and the thick oxide spacer transistor can be natively doped. The first and second thick oxide access transistors can be doped so as to have standard threshold voltage characteristics.
摘要翻译：包括厚氧化物间隔晶体管，与厚氧化物隔离晶体管相邻设置的可编程薄氧化物反熔丝以及第一和第二厚氧化物存取晶体管的可编程存储单元。厚氧化物间隔晶体管和第一和第二厚氧化物存取晶体管可以包括比可编程薄氧化物反熔丝的氧化物层厚的氧化物层。可编程薄氧化物反熔丝和厚氧化物间隔晶体管可以是本征掺杂的。可以掺杂第一和第二厚氧化物存取晶体管以具有标准阈值电压特性。

5. 发明授权

US08514637B2 Systems and methods of cell selection in three-dimensional cross-point array memory devices 有权
标题翻译：三维交叉点阵列存储器件中细胞选择的系统和方法
公开(公告)号：US08514637B2
公开(公告)日：2013-08-20
申请号：US12502111
申请日：2009-07-13
申请人： Chulmin Jung , Jinyoung Kim , Yong Lu , Harry Liu
发明人： Chulmin Jung , Jinyoung Kim , Yong Lu , Harry Liu
IPC分类号： G11C7/00
CPC分类号： G11C13/0023 , G11C5/02 , G11C13/0038 , G11C2213/71
摘要： Three dimensional cross-point array memory devices and selecting cells within a three dimensional cross-point array memory. In a particular embodiment, three different voltages levels are applied to bit lines of the cross point array to allow for selection of a specific cell. Series of select devices may be implemented to provide a high voltage and a low voltage to specific bit lines, while a middle voltage may also be provided. In a particular embodiment, the select devices comprise Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs).
摘要翻译：三维交叉点阵列存储器件，并选择三维交叉点阵列存储器内的单元。在特定实施例中，将三个不同的电压电平施加到交叉点阵列的位线以允许选择特定单元。可以实现一系列选择装置以向特定位线提供高电压和低电压，同时还可以提供中间电压。在特定实施例中，选择器件包括金属氧化物半导体场效应晶体管（MOSFET）。

6. 发明授权

US08367258B2 Electric power source arrangement and method of how to use it 有权
标题翻译：电源安排及使用方法
公开(公告)号：US08367258B2
公开(公告)日：2013-02-05
申请号：US12754001
申请日：2010-04-05
申请人： Zhijun Gu , Ke Jin , Yong Lu
发明人： Zhijun Gu , Ke Jin , Yong Lu
IPC分类号： H01M8/04
CPC分类号： H01M8/04559 , H01M8/0488 , H01M8/04955
摘要： An electric power source arrangement is described, comprising a fuel cell means (2) having a nominal voltage and a specified voltage-current characteristic, to be connected to a load (1), and comprising a variable DC-DC voltage converter (3), a by-pass branch (11) by-passing the DC-DC voltage converter, a switch (13) alternatively connecting the fuel cell to the DC-DC voltage converter or to the by-pass branch, and a control unit (12) controlling the switch, which control unit (12) comprises a measuring device coupled to the fuel cell means (2) for detecting the operating point thereof and is configured to connect the by-pass branch (11) if the fuel cell means voltage is within a selected range of section (5) of the voltage-current characteristic of the fuel cell means and to disconnect the by-pass branch in the remaining range of sections (4, 6, 7) of said characteristic.
摘要翻译：描述了一种电源装置，其包括具有额定电压和规定的电压 - 电流特性的燃料电池装置（2），连接到负载（1），并且包括可变DC-DC电压转换器（3），旁路分支（11）旁路DC-DC电压转换器，将燃料电池交替地连接到DC-DC电压转换器或旁路分支的开关（13），以及控制单元（12 ）控制所述开关，所述控制单元（12）包括联接到所述燃料电池单元（2）的测量装置，用于检测所述开关的工作点，并且如果所述燃料电池单元的电压为在燃料电池装置的电压 - 电流特性的部分（5）的选定范围内，并且在所述特性的部分（4,6,7）的剩余范围内断开旁路分支。

7. 发明授权

US08363449B2 Floating source line architecture for non-volatile memory 有权
标题翻译：用于非易失性存储器的浮动源线架构
公开(公告)号：US08363449B2
公开(公告)日：2013-01-29
申请号：US13206550
申请日：2011-08-10
申请人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C7/12 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C13/0069
摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an STRAM memory cell or an RRAM memory cell. In some embodiments, a plurality of N non-volatile memory cells, where N is a greater than two, are connected to a common floating source line. A write circuit is adapted to program a selected memory cell of the plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N−1 memory cells of the plurality via the common floating source line.
摘要翻译：用于将数据写入诸如STRAM存储器单元或RRAM存储器单元的非易失性存储单元的方法和装置。在一些实施例中，其中N大于2的多个N个非易失性存储器单元连接到公共的浮动源线。写入电路适于通过将所选择的大小的写入电流通过所选择的存储器单元来编程所选择的数据状态的所选择的存储单元，并且并行地通过所述剩余的N- 1个存储单元经由公共浮动源线。

8. 发明申请

US20130003448A1 MRAM DIODE ARRAY AND ACCESS METHOD 有权
标题翻译： MRAM二极管阵列和访问方法
公开(公告)号：US20130003448A1
公开(公告)日：2013-01-03
申请号：US13611225
申请日：2012-09-12
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
摘要翻译：存储单元包括磁性隧道结数据单元电耦合到位线和源极线。磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

9. 发明申请

US20120311399A1 MULTI-BIT ERROR CORRECTION METHOD AND APPARATUS BASED ON A BCH CODE AND MEMORY SYSTEM 审中-公开
标题翻译：基于BCH代码和存储器系统的多位错误校正方法和设备
公开(公告)号：US20120311399A1
公开(公告)日：2012-12-06
申请号：US13588700
申请日：2012-08-17
申请人： Yufei LI , Yong LU , Ying WANG , Hao YANG
发明人： Yufei LI , Yong LU , Ying WANG , Hao YANG
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/1575 , G06F11/10 , G11C2029/0411 , H03M13/152 , H03M13/1525 , H03M13/1565 , H03M13/17 , H03M13/3746
摘要： Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.
摘要翻译：提供了用于基于BCH码提供多位纠错的示例性实施例。在一个这样的实施例中，重复执行以下操作，包括将BCH码的每一位向右移位1位，同时填充由于BCH码中的向右移位而退出的位0，计算对应于 BCH码，并且基于与所述BCH码的移位相对应的校正子值，在所述移位下确定所述BCH码中的第一错误号。在第一错误号不等于0的情况下，对应于BCH码的移位来计算修正的综合征值。修正后的综合征值是对应于移位处的BCH码的当前最右边位置变为反向值的情况。如本文所述执行附加操作。

10. 发明授权

US08324607B2 Mirrored-gate cell for non-volatile memory 有权
标题翻译：用于非易失性存储器的镜像门单元
公开(公告)号：US08324607B2
公开(公告)日：2012-12-04
申请号：US13280392
申请日：2011-10-25
申请人： Roger Glenn Rolbiecki , Andrew Carter , Yong Lu
发明人： Roger Glenn Rolbiecki , Andrew Carter , Yong Lu
IPC分类号： H01L47/00
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11803 , H01L27/228 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233
摘要： A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate.
摘要翻译：一种存储器，包括至少一个可操作地连接到位线，源极线和字线的存储单元。存储单元包括具有第一源极触点，第二源极触点和第一源极触点和第二源极触点之间的位接触的基板，电连接第一源极触点和位触点的第一晶体管栅极和第二晶体管栅极电连接位触点和第二源触点。字线将第一晶体管栅极电连接到第二晶体管栅极。

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