专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5793315A Bit-serial digital expandor 失效
标题翻译：位串行数字扩展器
公开(公告)号：US5793315A
公开(公告)日：1998-08-11
申请号：US656131
申请日：1996-05-31
申请人： James Clark Baker
发明人： James Clark Baker
IPC分类号： H03H17/00 , H03G7/00 , H03G11/00 , H03M7/50 , H04B14/04
CPC分类号： H03G7/007 , H03G11/008
摘要： A bit-serial digital expandor includes a bit-serial dual scaler block (340), a bit-serial rectifier block (320), a bit-serial lowpass wave digital filter block (350), a bit-serial scaler with overflow detection block (360), a bit-serial multiplier block (380), and a bit-serial scaler and clipper block (395). This bit-serial expandor can be used in an AMPS cellular telephone receiver to produce a receiver having a lower silicon area, gate count, and current drain compared to equivalent parallel architecture receivers.
摘要翻译：位串行数字扩展器包括位串行双缩放器块（340），位串行整流器块（320），位串行低通波数字滤波器块（350），具有溢出检测块的比特串行缩放器（360），比特串行乘法器块（380）和比特串行缩放器和裁剪块（395）。与等效的并行架构接收器相比，该位串行扩展器可用于AMPS蜂窝式电话接收机中以产生具有较低硅面积，门数和电流消耗的接收机。

2. 发明授权

US06178186B1 Fractional decimator with linear interpolation and method thereof 失效
标题翻译：具有线性插值的分数抽取器及其方法
公开(公告)号：US06178186B1
公开(公告)日：2001-01-23
申请号：US09049624
申请日：1998-03-27
申请人： James Clark Baker , John Paul Oliver
发明人： James Clark Baker , John Paul Oliver
IPC分类号： H04J306
CPC分类号： H03H17/0685
摘要： According to the present disclosure, an parallel formatted data signal is applied to an input (300), and the data signal is divided into a first data signal and a second data signal. The second data signal is applied to a logic delay element (606) to produce a delayed second data signal that is a delayed-in-time version of the first data signal. The first data signal is applied to a first parallel-to-serial converter (706), the delayed second signal is applied to a second parallel-to-serial converter (708), and first and second bit-serial data streams are produced. A controller (710) synchronizes an Arithmetic Logic Unit (616) to the first and second bit-serial data streams so that the ALU (616) scales and sums the first and second bit-serial data streams to produce a bit-serial, sample-rate converted, output signal.
摘要翻译：根据本公开，并行格式化数据信号被施加到输入（300），并且数据信号被分成第一数据信号和第二数据信号。第二数据信号被施加到逻辑延迟元件（606）以产生延迟的第二数据信号，其是第一数据信号的延迟时间版本。第一数据信号被施加到第一并行到串行转换器（706），延迟的第二信号被施加到第二并行到串行转换器（708），并且产生第一和第二位串行数据流。控制器（710）将算术逻辑单元（616）同步到第一和第二位串行数据流，使得ALU（616）对第一和第二位串行数据流进行缩放和求和以产生位串行的样本 - 转换，输出信号。

3. 发明授权

US6073151A Bit-serial linear interpolator with sliced output 失效
标题翻译：具有切片输出的位串行线性内插器
公开(公告)号：US6073151A
公开(公告)日：2000-06-06
申请号：US106476
申请日：1998-06-29
申请人： James Clark Baker , Denise Carol Riemer , John Paul Oliver
发明人： James Clark Baker , Denise Carol Riemer , John Paul Oliver
IPC分类号： G06T3/40 , H03H17/06 , G06F7/38
CPC分类号： G06T3/4007 , H03H17/0657
摘要： Delayed versions of a bit-serial input sequence are created. When the interpolation involves scaled versions of the input sequence, scaled versions of the input sequence are produced. The interpolation equations are implemented by adding the delayed versions of the input sequence and the scaled versions of the input sequence together. The sign bit of each of the equated interpolation terms are applied to a multiplexer (528), and the sign bits are sequentially produced at the multiplexer output (529). The multiplexed sign bits are sequentially latched to the output of a latch (534) to produce the bit-serial interpolation with sliced output signal.
摘要翻译：创建位串行输入序列的延迟版本。当插值涉及输入序列的缩放版本时，产生输入序列的缩放版本。通过将输入序列的延迟版本和输入序列的缩放版本相加在一起来实现插值方程。每个等价内插项的符号位被施加到多路复用器（528），并且符号位在多路复用器输出（529）处顺序产生。多路复用的符号位被顺序锁存到锁存器的输出端（534），以产生具有分片输出信号的位串行插值。

4. 发明授权

US5903825A Digital FM receiver back end 失效
标题翻译：数字FM接收机后端
公开(公告)号：US5903825A
公开(公告)日：1999-05-11
申请号：US671385
申请日：1996-06-27
申请人： Steven Howard Goode , James Clark Baker , Michael John Carney
发明人： Steven Howard Goode , James Clark Baker , Michael John Carney
IPC分类号： H03D3/00 , H04B1/16
CPC分类号： H03D3/006
摘要： The digital FM receiver back end receives an analog intermediate frequency signal from a radio frequency front end (310) having a heterodyne circuit (312) and an intermediate frequency filter (314). In the receiver back end (307), a digital demodulator (330) having a hard limiter (333), a direct phase digitizer (336), and a phase differential circuit (339) produces a digital phase differential signal from the analog intermediate frequency signal. Next, a digital processor (360) filters and reduces noise in the digital phase differential signal using a bandpass filter (362), a de-emphasis filter (364), and an expandor (366). Finally, a pulse-width-modulation audio amplifier (380) prepares the signal for reproduction on an audio speaker (390). The digital FM receiver back end avoids inherent DC offset problems common to analog FM receivers, and it also offers a reduced complexity, size, and power consumption alternative to conventional digital FM receivers.
摘要翻译：数字FM接收机后端从具有外差电路（312）和中频滤波器（314）的射频前端（310）接收模拟中频信号。在接收机后端（307）中，具有硬限幅器（333），直接相位数字转换器（336）和相位差电路（339）的数字解调器（330）从模拟中频产生数字相位差分信号信号。接下来，数字处理器（360）使用带通滤波器（362），去加重滤波器（364）和扩展器（366）对数字相位差信号中的噪声进行滤波和降低。最后，脉冲宽度调制音频放大器（380）在音频扬声器（390）上准备用于再现的信号。数字FM接收机后端避免了模拟FM接收机常见的固有DC偏移问题，并且与传统的数字FM接收机相比，还提供了降低的复杂性，大小和功耗。

5. 发明授权

US06944402B1 Extended range infrared communication (ERIC) for an infrared associated (IrDA) compliant portable device 失效
标题翻译：用于红外相关（IrDA）兼容便携式设备的扩展范围红外通信（ERIC）
公开(公告)号：US06944402B1
公开(公告)日：2005-09-13
申请号：US09715672
申请日：2000-11-18
申请人： James Clark Baker , Steven Howard Goode , Henry Ludwig Kazecki
发明人： James Clark Baker , Steven Howard Goode , Henry Ludwig Kazecki
IPC分类号： H04B10/04 , H04B10/06 , H04B10/10
CPC分类号： H04B10/1143
摘要： An Infrared Data Association (IrDA) communication range (109) (e.g., 1 meter) of an IrDA compliant portable device (201) is increased to an extended range infrared communication (ERIC) range (209) (e.g., 2 to 40 meters) by extending a transmission range over an uplink channel (207) from the portable device (201) up to a base station (202) and by extending a transmission range over the downlink channel (208) from the base station (202) down to the portable device (201).
摘要翻译： IrDA兼容便携式设备（201）的红外数据协会（IrDA）通信范围（109）（例如，1米）增加到扩展范围红外通信（ERIC）范围（209）（例如，2至40米）通过将上行链路信道（207）上的传输范围从便携式设备（201）扩展到基站（202），并且通过将从下行链路信道（208）的传输范围从基站（202）扩展到基站便携式设备（201）。

6. 发明授权

US5754455A Method and apparatus for setting a bit-serial filter to an all-zero state 失效
标题翻译：将位串行滤波器设置为全零状态的方法和装置
公开(公告)号：US5754455A
公开(公告)日：1998-05-19
申请号：US631321
申请日：1996-04-10
申请人： James Clark Baker , Denise Carol Riemer
发明人： James Clark Baker , Denise Carol Riemer
IPC分类号： H03H17/02 , G06F17/10
CPC分类号： H03H17/0201
摘要： Bit-serial digital filters use numerous flip-flops, which must be reset to a known, all-zero state for testing and start-up purposes. A method for setting a bit-serial digital filter to an all-zero state uses non-resettable flip-flops, which eliminates the increased gate count and current drain overhead of resettable flip-flops. A bit-serial digital filter is constructed using non-resettable flip-flops such as simple non-resettable D flip-flops. When a reset signal is initiated, a reset controller (350) sends an all-zero signal to reset gates (301, 321) positioned at the input to the digital filter and in each feedback loop or unit-delay path. Meanwhile, a bit-serial controller (250) cycles through its control signals to emulate the operation of the bit-serial filter. In two word cycles, each flip-flop in the digital filter will be set to a known, all-zero state, and the all-zero signal is removed to allow normal operation of the filter.
摘要翻译：位串行数字滤波器使用大量触发器，必须将其复位到已知的全零状态，以便测试和启动目的。将位串行数字滤波器设置为全零状态的方法使用不可复位触发器，这消除了可复位触发器的增加的栅极数和电流消耗开销。使用非可复位触发器（例如简单的不可复位D触发器）来构造位串行数字滤波器。当启动复位信号时，复位控制器（350）将全零信号发送到位于数字滤波器的输入端和每个反馈回路或单位延迟路径中的复位门（301,321）。同时，位串行控制器（250）循环其控制信号以模拟位串行滤波器的操作。在两个字周期中，数字滤波器中的每个触发器将被设置为已知的全零状态，并且全零信号被去除以允许滤波器的正常操作。

7. 发明授权

US6072843A Method and apparatus for sigma-delta demodulator with aperiodic data 失效
标题翻译：具有非周期性数据的Σ-Δ解调器的方法和装置
公开(公告)号：US6072843A
公开(公告)日：2000-06-06
申请号：US13877
申请日：1998-01-27
申请人： James Clark Baker , John Paul Oliver , Nectar Andrew Kirkiris
发明人： James Clark Baker , John Paul Oliver , Nectar Andrew Kirkiris
IPC分类号： H03M3/02 , H03M7/32 , H04L27/00 , H03D1/00 , H03M1/00 , H03M3/00
CPC分类号： H04L27/0002 , H03M3/496 , H03M3/50
摘要： According to the present disclosure, aperiodic data is applied to parallel register (500). When a predetermined relationship between an aperiodic load signal and a periodic oversample clock signal occurs, the aperiodic data is latched to the output (506) of the parallel register as substantially periodic data. The substantially periodic data is loaded into a sigma-delta DAC (502) for processing. The sigma-delta DAC (502) is driven by a periodic oversample clock to produce a 1-bit oversampled, time averaged representation of the substantially periodic data.
摘要翻译：根据本公开，非周期性数据被应用于并行寄存器（500）。当发生非周期负载信号和周期性过采样时钟信号之间的预定关系时，非周期性数据被锁存到并行寄存器的输出端（506），作为基本上周期性的数据。基本上周期性的数据被加载到Σ-ΔDAC（502）中用于处理。 Σ-ΔDAC（502）由周期性过采样时钟驱动以产生基本周期性数据的1比特过采样的时间平均表示。

8. 发明授权

US5771182A Bit-serial digital compressor 失效
标题翻译：位串行数字压缩器
公开(公告)号：US5771182A
公开(公告)日：1998-06-23
申请号：US659104
申请日：1996-05-31
申请人： James Clark Baker , John Paul Oliver
发明人： James Clark Baker , John Paul Oliver
IPC分类号： H03G7/00 , H03G11/00 , H03M7/30 , G06F7/00 , G06F7/52 , G06F15/00 , G06M3/00
CPC分类号： H03G11/008 , H03G7/007 , H03M7/30
摘要： A bit-serial compressor (106) has a pre-divider circuit (208) receiving input serial data and generating a partial numerator. Divider circuit (210) divides the partial numerator by a denominator and generates a partial remainder that is fed back to the pre-divider circuit (208). Divider circuit (210) also generates serial data that is sent to an absolute value circuit (216) and then to a bit-serial filter (218). Bit-serial filter (218) generates an average signal from the serial data. A comparator circuit (224) compares the average signal to a threshold signal and generates the greater of the average signal or the threshold signal for use as a denominator in a next division cycle. The divider circuit includes an overflow control circuit (618) which detects overflow from the carryout bit of the partial remainder operation at the beginning of a division cycle and the sign bit of the numerator. If overflow is detected, the output is clipped according to whether the numerator is positive or negative.
摘要翻译：位串行压缩器（106）具有接收输入串行数据并产生部分分子的预分频器电路（208）。分频电路（210）将分数分母除以分母，并产生反馈到预分频器电路（208）的部分余数。分频电路（210）还产生发送到绝对值电路（216），然后发送到位串行滤波器（218）的串行数据。位串行滤波器（218）从串行数据生成平均信号。比较器电路（224）将平均信号与阈值信号进行比较，并产生平均信号或阈值信号中较大者，用于下一个分频周期中的分母。分频器电路包括溢出控制电路（618），该溢出控制电路（618）在分割周期开始时检测来自部分余数运算的进位位的溢出以及分子的符号位。如果检测到溢出，则根据分子是正还是负来剪切输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式