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1. 发明申请

US20180234101A1 DELAY-FREE POLY-PHASE QUANTIZER AND QUANTIZATION METHOD FOR PWM MISMATCH SHAPING 审中-公开
公开(公告)号：US20180234101A1
公开(公告)日：2018-08-16
申请号：US15435155
申请日：2017-02-16
申请人： QUALCOMM Incorporated
发明人： Jingxue Lu , Matthew Sienko
IPC分类号： H03M1/06 , H03M3/00
CPC分类号： H03M1/0617 , H03M3/42 , H03M3/432 , H03M3/47 , H03M3/50
摘要： A system and method for pulse-width modulation (PWM) mismatch shaping. The method includes receiving a multi-bit pulse-code modulated (PCM) signal and generating a voltage ramp signal. The method includes generating a first corrected signal based on a first feedback signal and the multi-bit PCM signal. The method includes generating a first single-bit PWM signal based on the first corrected signal and the voltage ramp signal. The method includes delaying the voltage-ramp signal and generating a second corrected signal based on a second feedback signal and the multi-bit PCM signal. The method includes generating a second single-bit PWM signal based on the second corrected signal and the delayed voltage ramp signal and generating a multi-bit pulse-density modulation (PDM) signal based on the first single-bit PWM signal and the second single-bit PWM signal.

2. 发明申请

US20180139802A1 WIRELESS ACCESS SYSTEM AND CONTROL METHOD FOR SAME 审中-公开
公开(公告)号：US20180139802A1
公开(公告)日：2018-05-17
申请号：US15569802
申请日：2016-03-07
申请人： NEC Corporation
发明人： Shinichi HORI , Tomoyuki YAMASE
IPC分类号： H04W88/08 , H03M3/00 , H03L7/08 , H04Q11/00 , H04B10/40
CPC分类号： H04W88/085 , H03L7/08 , H03L7/0807 , H03M3/02 , H03M3/30 , H03M3/40 , H03M3/458 , H03M3/50 , H04B1/40 , H04B10/25752 , H04B10/40 , H04B2210/006 , H04L27/36 , H04Q11/0067 , H04Q11/0071
摘要： Provided are a wireless access system provided with a remote unit capable of handling a high-frequency region without being made complicated, and a control method for the same. A wireless access system according to the present invention is provided with: a center unit (1); and a remote unit (3) that converts a baseband signal generated by the center unit (1) into a high-frequency signal and emits the high-frequency signal from an antenna (12). The center unit (1) includes a 1-bit modulator (5) that converts the baseband signal into a 1-bit signal on the basis of a generated clock signal and outputs the 1-bit signal. The remote unit (3) includes: a local generation unit (10) that extracts the clock signal from the 1-bit signal output from the center unit (1), and generates a local signal using the extracted clock signal as a reference signal; a filter (13) that extracts a desired band component from the 1-bit signal; and an up-converter (14) that converts, using the local signal, an output signal of the filter into a high-frequency signal.

3. 发明授权

US09941897B1 Digital-to-analog converter with improved linearity 有权
公开(公告)号：US09941897B1
公开(公告)日：2018-04-10
申请号：US15692812
申请日：2017-08-31
申请人： Analog Devices Global
发明人： Hongxing Li , Roberto Sergio Matteo Maurino
IPC分类号： H03M1/66 , H03M1/20 , H03M1/06 , H03M1/46
CPC分类号： H03M1/201 , H03M1/0639 , H03M1/0673 , H03M1/462 , H03M1/66 , H03M1/68 , H03M3/33 , H03M3/42 , H03M3/50
摘要： A higher accuracy ADC circuit (e.g., in which the number of bits of the ADC circuit is twelve or greater) may need calibration multiple times during its working life to avoid bit weight errors. Described are techniques to address DAC element ratio errors between DAC element clusters in a DAC circuit in order to maintain the linear performance of analog-to-digital converter (ADC) circuits and digital-to-analog converter (DAC) circuits.

4. 发明授权

US09853658B1 Digital to analog converter circuit and digital to analog conversion method 有权
公开(公告)号：US09853658B1
公开(公告)日：2017-12-26
申请号：US15639825
申请日：2017-06-30
申请人： RICHTEK TECHNOLOGY CORPORATION
发明人： Ming-Jun Hsiao , Zong-Yi Chen
IPC分类号： H03M3/00
CPC分类号： H03M3/50 , H03M1/504 , H03M3/438 , H03M3/506
摘要： A DAC circuit includes: a PWM encoding circuit for converting a digital signal to first and second PWM signals, whereby a combination of the first and second PWM signals becomes a PWM encoded signal of at least 3 levels including a positive, a zero and a negative level, wherein the digital signal represents a number in a numerical range; and a demodulation circuit for generating the analog signal according to the first and second PWM signals. The first and second PWM signals have a minimum duty larger than 0 when the digital signal represents a middle number in the numerical range. The zero level of the combination of the first and second PWM signals has a duty which decreases as a difference between the number represented by the digital signal and the middle number increases.

5. 发明授权

US09853657B2 Delta sigma modulator with dynamic error cancellation 有权
公开(公告)号：US09853657B2
公开(公告)日：2017-12-26
申请号：US15489124
申请日：2017-04-17
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Eeshan Miglani , Karthikeyan Gunasekaran , Santhosh Kumar Gowdhaman , Shagun Dusad
IPC分类号： H03M3/00 , H03M1/06 , H03M1/00 , H03M1/74 , H03M7/30 , H03M1/12
CPC分类号： H03M3/50 , H03M1/00 , H03M1/001 , H03M1/0626 , H03M1/0665 , H03M1/12 , H03M1/747 , H03M3/30 , H03M3/34 , H03M3/422 , H03M3/458 , H03M7/3004
摘要： The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.

6. 发明申请

US20170272045A1 ESTIMATING VOLTAGE ON SPEAKER TERMINALS DRIVEN BY A CLASS-D AMPLIFIER 审中-公开
公开(公告)号：US20170272045A1
公开(公告)日：2017-09-21
申请号：US15382159
申请日：2016-12-16
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Jasjot Singh CHADHA
IPC分类号： H03F3/217 , H04R3/04 , G11C27/02 , H04R29/00 , H03M3/00 , H03F3/183
CPC分类号： H03F3/2173 , H03F3/183 , H03F2200/03 , H03F2200/331 , H03F2200/351 , H03M3/50 , H04R3/002 , H04R3/04 , H04R29/001
摘要： A system includes an audio amplifier, a duty cycle detector, a channel equalizer, and a sample-and-hold circuit. The audio amplifier is configured to amplify an analog audio signal to produce an amplified audio signal. The duty cycle detector is configured to generate a saturation detect signal at a first state upon detection that the amplified audio signal produced by the audio amplifier is clipped. The channel equalizer is configured to generate an initial estimate of a speaker terminal voltage. The sample-and-hold circuit is configured to sample and hold the initial estimate of the speaker terminal voltage as a final estimate of the speaker voltage when the saturation detect signal is in the first state.

7. 发明授权

US09742427B2 Electrical circuit 有权
公开(公告)号：US09742427B2
公开(公告)日：2017-08-22
申请号：US15151236
申请日：2016-05-10
申请人： Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
发明人： Michael Hackner , Hans-Peter Hohe , Markus Sand
IPC分类号： H03M3/02 , H03M3/00 , H03M1/12 , H03M1/82 , H03M7/30 , H03L7/08 , H03M1/50
CPC分类号： H03M3/39 , H03L7/08 , H03M1/1255 , H03M1/50 , H03M1/82 , H03M3/462 , H03M3/496 , H03M3/50 , H03M7/3004
摘要： An electrical circuit includes a signal processing chain and a controller. The signal processing chain includes an integrator configured to integrate an input signal over an integration time. The controller is connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain. The controller is further configured to adapt the integration time based on the output signal.

8. 发明授权

US09685975B2 Distributed combiner for parallel discrete-to-linear converters 有权
公开(公告)号：US09685975B2
公开(公告)日：2017-06-20
申请号：US14996497
申请日：2016-01-15
申请人： Syntropy Systems, LLC
发明人： Christopher Pagnanelli
IPC分类号： G06F7/42 , H03M1/66 , H03F3/21 , H03M1/08 , H03M3/00
CPC分类号： H03M1/661 , H03F3/211 , H03M1/08 , H03M1/0836 , H03M1/662 , H03M3/30 , H03M3/50
摘要： Provided are, among other things, systems, apparatuses methods and techniques for providing a complete output signal from a set of partial signals, which in turn have been generated by parallel processing paths in the time-interleaved and/or frequency-interleaved conversion of discrete signals to linear signals (i.e., discrete-to-linear conversion). One such apparatus includes a distributed network comprising a plurality of ladder networks through which input signals propagate before being combined to form an output signal.

9. 发明申请

US20170134040A1 ASYNCHRONOUS ELECTRICAL CIRCUITRY TECHNIQUES FOR PRODUCING STATIONARY CARRIER SIGNAL TO ENCODE INPUT SIGNAL AMPLITUDE INTO OUTPUT SIGNAL TIME-SEQUENCE INFORMATION 有权
公开(公告)号：US20170134040A1
公开(公告)日：2017-05-11
申请号：US15323038
申请日：2015-06-30
申请人： Indice Semiconductor Inc.
发明人： James Hamond , Robert D. Batten
IPC分类号： H03M3/00
CPC分类号： H03M3/50 , H03M3/32 , H03M3/37 , H03M3/39 , H03M3/402 , H03M3/43 , H03M3/458
摘要： Asynchronous electrical circuitry (400, 500, 600, 700, 800, 900) produces a stationary carrier signal (470, 470′) and encodes a system input signal (460, 460′) amplitude into output signal time-sequence information by establishing at a digitizer (410, 510, 610, 710, 810, 910) an operating point value (416, 516, 616, 716, 816, 916) as an average amplitude of the system input signal. It applies to the digitizer a multicomponent digitizer-input signal (470, 470′) corresponding to a sum of a passband signal component and a feedback signal component to produce a pulse-width modulated digitizer output signal (480, 480′) representing the system input signal. An asynchronous time delay (t(s)) is introduced to produce the pulse-width modulated system output signal (y(s)). The circuitry performs digital to analog conversion (DAC) to the pulse-width modulated system output signal to produce a DAC output signal (490, 490′). The DAC output signal or its summation with the passband signal component is integrated to produce the feedback signal component. Additional, multiple-order embodiments include sequential feedback paths or carrier-shaping functions.

10. 发明申请

US20170019123A1 DELTA SIGMA MODULATOR FOR SHAPING NOISE AND AUDIO CODEC HAVING THE SAME 有权
标题翻译：用于形成噪声的DELTA SIGMA调制器和具有该噪声的音频编码
公开(公告)号：US20170019123A1
公开(公告)日：2017-01-19
申请号：US15097715
申请日：2016-04-13
申请人： Samsung Electronics Co., Ltd.
发明人： Mooyeol Choi , Hyungdong Roh , Bai-Sun Kong , Sunwoo Kwon , Myung-Jin Lee
IPC分类号： H03M3/00 , G06F3/16
CPC分类号： H03M3/422 , G06F3/162 , H03M1/464 , H03M3/372 , H03M3/50
摘要： A delta-sigma modulator includes a loop filter, a quantizer configured to change an analog output signal into a digital signal, and a digital-to-analog converter configured to receive the digital signal and including a first capacitor and a second capacitor. In a first sampling period, the first capacitor is discharged, and at the same time, the second capacitor is charged with a reference voltage. In a second sampling period, the digital signal includes noise caused by a clock jitter, the first capacitor is charged with a reference voltage, and the second capacitor is discharged and generates a charge corresponding to the noise. In a next first sampling period, the first capacitor is discharged, and at the same time, the second capacitor generates a noise current corresponding to the noise using the charge and is charged with a reference voltage.
摘要翻译： Δ-Σ调制器包括环路滤波器，被配置为将模拟输出信号改变为数字信号的量化器，以及被配置为接收数字信号并包括第一电容器和第二电容器的数/模转换器。在第一采样周期中，第一电容器被放电，同时第二电容器被充以基准电压。在第二采样周期中，数字信号包括由时钟抖动引起的噪声，第一电容器用参考电压充电，并且第二电容器被放电并产生对应于噪声的电荷。在接下来的第一采样周期中，第一电容器被放电，并且同时第二电容器使用电荷产生与噪声相对应的噪声电流并且对基准电压进行充电。

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