专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06636372B1 Accumulating read channel performance data 有权
标题翻译：累积读通道性能数据
公开(公告)号：US06636372B1
公开(公告)日：2003-10-21
申请号：US09550440
申请日：2000-04-17
申请人： Dat Nguyen , James Wilson Rae
发明人： Dat Nguyen , James Wilson Rae
IPC分类号： G11B509
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/182 , G11B20/1879 , G11B27/36 , G11B2220/20
摘要： Systems and methods for accumulating data relating to the performance of one or more components of a read channel are described. In one aspect, a programmable channel quality monitor is operable to accumulate performance data corresponding to a recorded test data sequence spanning two or more data sectors of the magnetic medium. The channel quality monitor preferably is incorporated in a disk drive system. A method of accumulating performance data from a read channel also is described. In accordance with this inventive method, an original test data pattern is written to multiple data sectors of the magnetic medium. The original test pattern is read from the multiple data sectors of the magnetic medium to produce a readback test pattern. In this method, performance data relating to a comparison of the original test pattern and the readback test pattern is accumulated.
摘要翻译：描述用于累积与读取通道的一个或多个组件的性能有关的数据的系统和方法。在一个方面，可编程信道质量监视器可操作以累积对应于跨越磁介质的两个或多个数据扇区的记录测试数据序列的性能数据。通道质量监视器优选地并入磁盘驱动系统中。还描述了从读取通道累加性能数据的方法。根据本发明的方法，将原始测试数据模式写入磁介质的多个数据扇区。从磁介质的多个数据扇区读取原始测试图案以产生回读测试图案。在该方法中，累积与原始测试图案和回读测试图案的比较有关的性能数据。

2. 发明申请

US20090302904A1 Phase Frequency Detector Circuit for Implementing Low PLL Phase Noise and Low Phase Error 审中-公开
标题翻译：用于实现低PLL相位噪声和低相位误差的相位检波器电路
公开(公告)号：US20090302904A1
公开(公告)日：2009-12-10
申请号：US12136218
申请日：2008-06-10
申请人： Darrell Lee Livezey , James Wilson Rae , Patrick Lee Rosno , Timothy Joseph Schmerbeck
发明人： Darrell Lee Livezey , James Wilson Rae , Patrick Lee Rosno , Timothy Joseph Schmerbeck
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03D13/004 , H03L7/093
摘要： A method and Phase Frequency Detector (PFD) circuit for implementing low phase locked loop (PLL) phase noise and low phase error, and a design structure on which the subject circuit resides are provided. The PFD circuit includes a PFD latch receiving clock and reset signals, and PFD output driver circuit providing PFD output signals. The PFD latch is set by the clock and reset by the reset signal. An AND gate coupled to the PFD latch and the PFD output driver circuit includes differential inputs and outputs and applies the reset signal to the PFD latch. The PFD latch, AND gate and PFD output driver circuit are formed by current mode logic using bipolar transistors. An active loop filter generates a tuning voltage output.
摘要翻译：一种用于实现低锁相环（PLL）相位噪声和低相位误差的方法和相位频率检测器（PFD）电路，以及提供主题电路所在的设计结构。 PFD电路包括PFD锁存器接收时钟和复位信号，PFD输出驱动电路提供PFD输出信号。 PFD锁存器由时钟设置，并由复位信号复位。耦合到PFD锁存器和PFD输出驱动器电路的与门包括差分输入和输出，并将复位信号施加到PFD锁存器。 PFD锁存器，与门和PFD输出驱动器电路由使用双极晶体管的电流模式逻辑形成。有源环路滤波器产生调谐电压输出。

3. 发明授权

US06661590B2 Efficient analog front end for a read/write channel of a hard disk drive running from a highly regulated power supply 有权
公开(公告)号：US06661590B2
公开(公告)日：2003-12-09
申请号：US09865860
申请日：2001-05-25
申请人： Sasan Cyrusian , Stephen J. Franck , Sriharsha Annadore , Elmar Bach , Siegfried Hart , Thomas Blon , William G. Bliss , James Wilson Rae , Michael Ruegg , Ulrich Huewels , Fritz Mistlberger
发明人： Sasan Cyrusian , Stephen J. Franck , Sriharsha Annadore , Elmar Bach , Siegfried Hart , Thomas Blon , William G. Bliss , James Wilson Rae , Michael Ruegg , Ulrich Huewels , Fritz Mistlberger
IPC分类号： G11B509
CPC分类号： G11B5/02 , G11B5/012 , G11B20/10009
摘要： A method and apparatus for running an analog portion (162) of a read/write channel (108) from a highly regulated power supply (260). The apparatus includes an analog portion (162), a clock synthesizer (154), and a highly regulated power supply (260) connected to the analog portion (162) and the clock synthesizer (154). The analog portion (162) and the clock synthesizer (154) both comprise high voltage transistors which operate in a first voltage range and low voltage transistors which operate in a second voltage range, wherein the first voltage range is within the second voltage range. The highly regulated power supply (260) supplies power that is within the first voltage range to the analog portion (162) and the clock synthesizer (154). The method includes generating power that is within the first voltage range using the highly regulated power supply (260), and supplying the power to the analog portion (162) and the clock synthesizer (154).

4. 发明授权

US06587292B1 Magneto-resistive asymmetry compensation loop 有权
标题翻译：磁阻不对称补偿回路
公开(公告)号：US06587292B1
公开(公告)日：2003-07-01
申请号：US09546796
申请日：2000-04-11
申请人： Jonathan Ashley , James Wilson Rae , Stephen J. Franck
发明人： Jonathan Ashley , James Wilson Rae , Stephen J. Franck
IPC分类号： G11B5035
CPC分类号： G11B20/10055 , G11B5/09 , G11B20/10009 , G11B20/22
摘要： A magneto-resistive asymmetry compensation system includes a linearizer (61) interposed in a data path and a control loop (63). The control loop uses signal estimates from an interpolated timing response unit (25) to derive a magneto-resistive asymmetry error. The error term is used to obtain a control scaling input to the linearizer. The linearizer functions to multiply the scaling multiple to the square of the input signal and then add it back to the input signal.
摘要翻译：磁阻非对称补偿系统包括插入在数据路径中的线性化器（61）和控制回路（63）。控制环路使用来自内插定时响应单元（25）的信号估计来导出磁阻非对称误差。误差项用于获得对线性化器的控制缩放输入。线性化器用于将缩放倍数乘以输入信号的平方，然后将其添加回输入信号。

5. 发明授权

US4042883A Automatic noise limiter 失效
标题翻译：自动噪音限制器
公开(公告)号：US4042883A
公开(公告)日：1977-08-16
申请号：US670503
申请日：1976-03-25
申请人： James Wilson Rae
发明人： James Wilson Rae
IPC分类号： H03G3/34 , H03G11/02 , H03G11/04 , H04B1/10
CPC分类号： H04B1/1027 , H03G3/345
摘要： The output from a peak detector of a conventional radio receiver includes a recovered audio signal and a DC level. The disclosed noise limiter processes the detector output through both low pass and high pass filters. The low pass filter produces a DC signal representative of both the detector DC level and the recovered audio signal level. The high pass filter passes only the recovered audio signal. A semiconductor diode connects between the filter outputs, and the output of the noise limiter. For peak detector levels at, or below the 100% modulation level the diode is forward biased and passes the audio signal to the noise limiter output for further receiver processing. Peak detector levels exceeding 100% modulation, such as noise, reverse bias the diode whereby the audio signal is blocked from subsequent receiver stages.
摘要翻译：来自常规无线电接收机的峰值检测器的输出包括恢复的音频信号和DC电平。所公开的噪声限制器通过低通滤波器和高通滤波器处理检测器输出。低通滤波器产生代表检测器DC电平和恢复的音频信号电平的DC信号。高通滤波器仅通过恢复的音频信号。半导体二极管连接在滤波器输出端和噪声限制器的输出端之间。对于或低于100％调制电平的峰值检测器电平，二极管正向偏置，并将音频信号传递到噪声限制器输出，以进一步接收器处理。峰值检测器电平超过100％调制，例如噪声，二极管反向偏置，从而音频信号从后续接收器级阻挡。

6. 发明授权

US5796358A Methods and structure for combined analog and digital automatic gain control in sampled-data receivers 失效
标题翻译：采样数据接收机中组合模拟和数字自动增益控制的方法和结构
公开(公告)号：US5796358A
公开(公告)日：1998-08-18
申请号：US693587
申请日：1996-08-01
申请人： Shih-Ming Shih , James Wilson Rae , Richard A. Contreras , Jenn-Gang Chern
发明人： Shih-Ming Shih , James Wilson Rae , Richard A. Contreras , Jenn-Gang Chern
IPC分类号： H03M1/18 , H03M1/00
CPC分类号： H03M1/183
摘要： Analog-to-digital (ADC) output bits are partitioned in a way that simplifies the gain error calculations. Simplification of the gain error calculations allows a reduction in the complexity of the circuits needed to implement automatic gain control (AGC).
摘要翻译：模数（ADC）输出位以简化增益误差计算的方式进行分区。增益误差计算的简化可以降低实现自动增益控制（AGC）所需电路的复杂度。

7. 发明授权

US06816328B2 Pseudo-synchronous interpolated timing recovery for a sampled amplitude read channel 有权
标题翻译：采样振幅读通道的伪同步内插定时恢复
公开(公告)号：US06816328B2
公开(公告)日：2004-11-09
申请号：US09882084
申请日：2001-06-13
申请人： James Wilson Rae
发明人： James Wilson Rae
IPC分类号： G11B509
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B20/1426
摘要： Systems and methods for reading information stored on a magnetic medium are described. Data symbols are generated from a signal encoded at a baud rate with data including an acquisition preamble defining an acquisition frequency and an acquisition phase. The system includes an inventive dual loop synchronizer that is optimized to improve the operating efficiency and reduce the overall latency of the read channel. In one aspect, the dual loop synchronizer includes a frequency synchronization loop, a signal sampler, an interpolator, and a phase synchronization loop. The frequency synchronization loop is configured to generate a sampling clock synchronized approximately to the acquisition frequency and the acquisition phase of the encoded data signal. The signal sampler is coupled to the frequency synchronization loop and is configured to sample the encoded data signal in response to the sampling clock to produce a plurality of data samples. The interpolator is coupled to the frequency synchronization loop and is configured to produce in response to the sampling clock interpolated samples from the data samples. The phase synchronization loop is coupled to the interpolator and is configured to synchronize the interpolator to the baud rate of the encoded data signal. In another aspect, the frequency synchronization loop includes a delay-locked loop configured to synthesize the sampling clock.
摘要翻译：描述用于读取存储在磁性介质上的信息的系统和方法。从波特率编码的信号产生数据符号，数据包括定义采集频率和采集阶段的采集前导码。该系统包括本发明的双回路同步器，其被优化以提高操作效率并降低读取通道的总体等待时间。一方面，双回路同步器包括频率同步回路，信号取样器，内插器和相位同步回路。频率同步环路被配置为产生大致与编码数据信号的采集频率和采集相位同步的采样时钟。信号采样器耦合到频率同步环路，并被配置为响应于采样时钟采样编码数据信号以产生多个数据样本。内插器耦合到频率同步环路，并被配置为响应于来自数据样本的采样时钟内插采样而产生。相位同步环耦合到内插器，并且被配置为使内插器与编码数据信号的波特率同步。在另一方面，频率同步环路包括被配置为合成采样时钟的延迟锁定环路。

8. 发明授权

US06408419B1 Trellis code for extended partial response maximum likelihood (EPRML) channel 有权
标题翻译：扩展部分响应最大似然（EPRML）通道的格子码
公开(公告)号：US06408419B1
公开(公告)日：2002-06-18
申请号：US09347598
申请日：1999-07-01
申请人： Razmik Karabed , Jonathan J. Ashley , James Wilson Rae
发明人： Razmik Karabed , Jonathan J. Ashley , James Wilson Rae
IPC分类号： H03M1300
CPC分类号： H04L1/0059 , H04L25/03178 , H04L25/497
摘要： A first trellis code (12A, 20A) according to the present invention is a rate 24/26 trellis code with three (3) bytes error propagation due to EPRML minimum instance channel errors, a minimum of six (6) transitions per code word and a maximum of twelve (12) consecutive zeroes. A second trellis code (12B, 20B) according to the present invention is a rate 48/51 trellis code, derived from the first trellis code. The second trellis code has four (4) bytes error propagation due to EPRML minimum distance channel errors, a minimum of twelve (12) transitions per code word and a maximum of twelve (12) consecutive zeroes. A third trellis code (12C, 20C) according to the present invention is a rate 48/51 trellis code with four (4) bytes error propagation due to EPRML minimum distance channel errors, a minimum of fourteen (14) transitions per code word and a maximum of eleven (11) consecutive zeroes.
摘要翻译：根据本发明的第一网格码（12A，20A）是由于EPRML最小实例信道错误而导致的三（3）字节错误传播的速率为24/26格状码，每码字最少六（6）个转换，最多十二（12）个连续零。根据本发明的第二网格码（12B，20B）是从第一网格码导出的速率48/51网格码。由于EPRML最小距离信道错误，每个码字最少十二（12）个转换和最多十二（12）个连续零点，第二个网格码具有四（4）个字节的错误传播。根据本发明的第三网格码（12C，20C）是由于EPRML最小距离信道误差而导致四（4）字节错误传播的速率48/51格状码，每码字最少十四（14）个转换，最多十一（11）个连续零。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式