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1. 发明授权

US06745362B1 Method and device for error correction coding and corresponding decoding method and device 有权
标题翻译：纠错编码方法和装置及相应的解码方法及装置
公开(公告)号：US06745362B1
公开(公告)日：2004-06-01
申请号：US09744849
申请日：2001-03-22
申请人： Jean-Claude Carlach , Cyril Vervoux
发明人： Jean-Claude Carlach , Cyril Vervoux
IPC分类号： H03M1305
CPC分类号： H03M13/27 , H03M13/136 , H03M13/2906
摘要： The invention concerns a method and a device for error correction coding associating with a data source series a coded data block, to be transmitted to at least one receiver comprising at least two coding stages (21i) each comprising at least two basic coding modules (22i,j), each of said coding stages receiving a series of data to be processed, distributed between said basic coding modules, and delivering a series of processed data, derived from said basic coding modules and at least one branching stage (23i), said branching stage being inserted between two successive coding stages, a first coding stage and a second coding stage, and distributing the processed data derived from each basic coding module of said first coding stage between at least two basic coding modules of said second stage. The invention also concerns the corresponding decoding method and device, based on path likelihood.
摘要翻译：本发明涉及一种用于纠错编码的方法和装置，其将数据源序列与编码数据块相关联，所述编码数据块将发送到包括至少两个编码级（21i）的至少一个接收机，每个编码级包括至少两个基本编码模块（22i ，j）中，每个所述编码级接收一系列要处理的数据，分布在所述基本编码模块之间，并且从所述基本编码模块和至少一个分支级（23i）导出的一系列处理数据，以及在两个连续编码级之间插入分支级，第一编码级和第二编码级，并将从所述第一编码级的每个基本编码模块导出的处理数据分配在所述第二级的至少两个基本编码模块之间。本发明还涉及基于路径可能性的相应的解码方法和装置。

2. 发明授权

US4841462A Random access memory and linear interpolation circuit comprising application thereof 失效
标题翻译：随机存取存储器和包括其应用的线性内插电路
公开(公告)号：US4841462A
公开(公告)日：1989-06-20
申请号：US800413
申请日：1985-11-21
申请人： Jean-Pierre Vigarie , Jean-Claude Carlach , Pierre Penard
发明人： Jean-Pierre Vigarie , Jean-Claude Carlach , Pierre Penard
IPC分类号： G06F17/17 , G11C8/10 , G11C11/419
CPC分类号： G06F17/17 , G11C11/419 , G11C8/10 , Y10S257/903
摘要： A random access memory (RAM) comprises memory cells each including an RS type flip-flop having complementary data inputs and transistors for forcing the flip-flop by that one of two data wires which is at a given level (high level for example) when a selection wire is at a first given level (high level for example). The flip-flop is connected to an output wire by circuitry for maintaining the output wire at the high level as long as the selection wire is at the first level and for causing the output wire to take the level corresponding to the condition of the flip-flop when the selection wire is brought to the other level. The transistors are preferably N-MOS for higher speed.
摘要翻译：随机存取存储器（RAM）包括存储单元，每个存储单元包括具有互补数据输入的RS型触发器和晶体管，用于通过位于给定电平（例如高电平）的两条数据线之一强制触发器，选择线处于第一给定水平（例如，高水平）。触发器通过电路连接到输出线，用于将输出线保持在高电平，只要选择线处于第一电平并且使输出线获得与触发器的状态相对应的电平，当选择线被带到另一个水平时翻转。晶体管优选用于更高速度的N-MOS。

3. 发明授权

US09100048B2 Method and device for transmission and reception in a multi-input and multi-output channel distributing a code word between several mapping matrices, and corresponding computer program 有权
标题翻译：用于在多输入和多输出通道中发送和接收的方法和装置，其在多个映射矩阵之间分配码字，以及相应的计算机程序
公开(公告)号：US09100048B2
公开(公告)日：2015-08-04
申请号：US13819605
申请日：2011-08-29
申请人： Jean-Claude Carlach , Ali El Arab , Maryline Helard
发明人： Jean-Claude Carlach , Ali El Arab , Maryline Helard
IPC分类号： H03M13/05 , H04L1/00 , H04L1/06 , H04L25/03 , H04L25/497 , H04B7/04
CPC分类号： H03M13/05 , H04B7/0413 , H04L1/0057 , H04L1/06 , H04L25/03343 , H04L25/497 , H04L2025/03426
摘要： A method for transmitting a source binary sequence, including at least one source word, in a transmission channel. The method includes the following steps, for at least one source word: error-correcting encoding the source word, outputting a code word; matrix mapping the code word, distributing bits constituting the code word within at least two mapping matrices, which are reversible and observe a criterion of uniqueness in the cancellation of a syndrome associated with the code word; and consecutively transmitting the at least two mapping matrices.
摘要翻译：一种用于在传输信道中发送包括至少一个源字的源二进制序列的方法。该方法包括以下步骤：对于至少一个源字：对源字进行纠错编码，输出码字; 矩阵映射码字，在至少两个映射矩阵内分配构成码字的位，其是可逆的，并且在取消与码字相关联的综合征中观察到唯一性的标准; 以及连续发送所述至少两个映射矩阵。

4. 发明授权

US08549365B2 Method and device for flexible error correction encoding and corresponding computer program 有权
标题翻译：用于灵活纠错编码的方法和装置及相应的计算机程序
公开(公告)号：US08549365B2
公开(公告)日：2013-10-01
申请号：US13147355
申请日：2010-02-01
申请人： Jean-Claude Carlach
发明人： Jean-Claude Carlach
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H03M13/136 , H03M13/19 , H03M13/27 , H03M13/2785 , H03M13/6561
摘要： An error correction encoding device is provided that combines redundancy data with source data, said device including: at least three encoding stages and at least two permutation stages. Each encoding stage implements at least one set of three basic encoding modules, in which a first encoding stage receives said source data and a last encoding stage provides said redundancy data. Each encoding module implements a basic code and includes c inputs and c outputs, c being an integer. The permutation stages are inserted between two consecutive encoding stages and each permutation stage implements a c-cyclic permutation.
摘要翻译：提供了一种组合冗余数据与源数据的纠错编码装置，所述装置包括：至少三个编码级和至少两个置换级。每个编码级实现至少一组三个基本编码模块，其中第一编码级接收所述源数据，最后编码级提供所述冗余数据。每个编码模块实现基本代码，并包括c个输入和c个输出，c是一个整数。置换级插入两个连续编码级之间，每个置换级实现c-循环置换。

5. 发明申请

US20130159817A1 METHOD AND DEVICE FOR TRANSMISSION AND RECEPTION IN A MULTI-INPUT AND MULTI-OUTPUT CHANNEL DISTRIBUTING A CODE WORD BETWEEN SEVERAL MAPPING MATRICES, AND CORRESPONDING COMPUTER PROGRAM 有权
标题翻译：用于在多输入和多输出通道中传输和接收的方法和装置分配几个映射矩阵之间的代码字，以及对应的计算机程序
公开(公告)号：US20130159817A1
公开(公告)日：2013-06-20
申请号：US13819605
申请日：2011-08-29
申请人： Jean-Claude Carlach , Ali El Arab , Maryline Helard
发明人： Jean-Claude Carlach , Ali El Arab , Maryline Helard
IPC分类号： H03M13/05
CPC分类号： H03M13/05 , H04B7/0413 , H04L1/0057 , H04L1/06 , H04L25/03343 , H04L25/497 , H04L2025/03426
摘要： A method for transmitting a source binary sequence, including at least one source word, in a transmission channel, The method includes the following steps, for at least one source word: error-correcting encoding the source word, outputting a code word; matrix mapping the code word, distributing bits constituting the code word within at least two mapping matrices, which are reversible and observe a criterion of uniqueness in the cancellation of a syndrome associated with the code word; and consecutively transmitting the at least two mapping matrices.
摘要翻译：一种用于在传输信道中发送包括至少一个源字的源二进制序列的方法。所述方法包括以下步骤：对于至少一个源字：对源字进行纠错编码，输出码字; 矩阵映射码字，在至少两个映射矩阵内分配构成码字的位，其是可逆的，并且在取消与码字相关联的综合征中观察到唯一性的标准; 以及连续发送所述至少两个映射矩阵。

6. 发明申请

US20110289367A1 METHOD AND DEVICE FOR FLEXIBLE ERROR CORRECTION ENCODING AND CORRESPONDING COMPUTER PROGRAM 有权
标题翻译：用于灵活纠错编码和对应计算机程序的方法和装置
公开(公告)号：US20110289367A1
公开(公告)日：2011-11-24
申请号：US13147355
申请日：2010-02-01
申请人： Jean-Claude Carlach
发明人： Jean-Claude Carlach
IPC分类号： H03M13/19
CPC分类号： H03M13/136 , H03M13/19 , H03M13/27 , H03M13/2785 , H03M13/6561
摘要： An error correction encoding device is provided that combines redundancy data with source data, said device including: at least three encoding stages and at least two permutation stages. Each encoding stage implements at least one set of three basic encoding modules, in which a first encoding stage receives said source data and a last encoding stage provides said redundancy data. Each encoding module implements a basic code and includes c inputs and c outputs, c being an integer. The permutation stages are inserted between two consecutive encoding stages and each permutation stage implements a c-cyclic permutation.
摘要翻译：提供了一种组合冗余数据与源数据的纠错编码装置，所述装置包括：至少三个编码级和至少两个置换级。每个编码级实现至少一组三个基本编码模块，其中第一编码级接收所述源数据，最后编码级提供所述冗余数据。每个编码模块实现基本代码，并包括c个输入和c个输出，c是一个整数。置换级插入两个连续编码级之间，每个置换级实现c-循环置换。

7. 发明授权

US4696020A Digital circuit for frequency or pulse rate division 失效
标题翻译：用于频率或脉冲分频的数字电路
公开(公告)号：US4696020A
公开(公告)日：1987-09-22
申请号：US909027
申请日：1986-09-17
申请人： Jean-Claude Carlach
发明人： Jean-Claude Carlach
IPC分类号： H03K23/52 , G06F7/68 , H03K3/356 , H03K23/00 , H03K23/54 , H03K23/66 , H03K23/48
CPC分类号： H03K23/546 , G06F7/68 , H03K23/66 , H03K3/356017
摘要： The digital circuit is for receiving a master clock signal at a frequency te f on an input and delivering a rectangular shaped output signal at a lower frequency (M/N)f where M is an integer and N is an even integer greater than M. The circuit comprises an even number N of series connected flip-flops in a ring arrangement, each flip-flop being connected to receive input signals from the preceding flip-flop and from the following flip-flop and to receive a master clock signal on a clock input. The even numbered flip-flops are of a type different from the type of the odd numbered flip-flops. The outputs of the flip-flops each deliver a rectangular pulse signal having a duty ratio equal to 1/N of that of the master clock signal. The pulse signals are applied to a combination logic of OR type giving an output signal combining the outputs of said plurality of flip-flops.
摘要翻译：数字电路用于以输入端的频率f接收主时钟信号，并以较低频率（M / N）f传送矩形输出信号，其中M为整数，N为大于M的偶数整数。该电路包括偶数N个以环形布置的串联连接的触发器，每个触发器被连接以接收来自先前触发器和下一个触发器的输入信号，并且接收主时钟信号时钟输入。偶数触发器的类型与奇数触发器的类型不同。触发器的输出各自递送具有等于主时钟信号的占空比的1 / N的矩形脉冲信号。脉冲信号被施加到或类型的组合逻辑，给出组合所述多个触发器的输出的输出信号。

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