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1. 发明授权

US07757135B2 Method and apparatus for storing and distributing memory repair information 有权
标题翻译：用于存储和分发存储器修复信息的方法和装置
公开(公告)号：US07757135B2
公开(公告)日：2010-07-13
申请号：US11853383
申请日：2007-09-11
申请人： Benoit Nadeau-Dostie , Jean-François Coté
发明人： Benoit Nadeau-Dostie , Jean-François Coté
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/4401 , G11C29/802 , G11C2029/0401 , G11C2029/4402 , G11C2229/726
摘要： A system for repairing embedded memories on an integrated circuit includes an external Built-In Self-repair Register (BISR) associated with every reparable memory. Each BISR is serially configured in a daisy chain with a fuse box controller. The controller determines the daisy chain length upon power up. The controller may perform a corresponding number of shift operations to move repair data between BISRs and a fuse box. Memories can have a parallel or serial repair interface. The BISRs may have a repair analysis facility into which fuse data may be dumped and uploaded to the fuse box or downloaded to repair the memory. Pre-designed circuit blocks provide daisy chain inputs and access ports to effect the system or to bypass the circuit block.
摘要翻译：用于在集成电路上修复嵌入式存储器的系统包括与每个可修复存储器相关联的外部内置自修复寄存器（BISR）。每个BISR以一个带有保险丝盒控制器的菊花链串行配置。控制器在上电时确定菊花链长度。控制器可以执行相应数量的换档操作，以在BISR和保险丝盒之间移动修理数据。存储器可以具有并行或串行修复界面。 BISR可能有一个维修分析设备，熔断器数据可能被转储并上传到保险丝盒或下载以修复存储器。预先设计的电路块提供菊花链输入和访问端口来影响系统或绕过电路块。

2. 发明授权

US06327684B1 Method of testing at-speed circuits having asynchronous clocks and controller for use therewith 有权
标题翻译：测试具有异步时钟的高速电路的方法和与其一起使用的控制器
公开(公告)号：US06327684B1
公开(公告)日：2001-12-04
申请号：US09309827
申请日：1999-05-11
申请人： Benoit Nadeau-Dostie , Naader Hasani , Jean-François Coté
发明人： Benoit Nadeau-Dostie , Naader Hasani , Jean-François Coté
IPC分类号： G01R3128
CPC分类号： G01R31/318563 , G01R31/3016 , G01R31/31858 , G01R31/318594
摘要： A method of testing the core logic in a digital system, the method having a sequence of test operations including a shift-in operation in which a test stimulus is shifted into scanable memory elements in the core logic, a capture operation in which data in the memory elements is captured, and a shift-out operation in which captured data is shifted out of the core logic for analysis, comprises the improvement of, for each the test operation, concurrently enabling the domain clock of each clock domain in the core logic at the beginning of each test operation, performing the test operation in each domain and disabling the domain clock at the end of each test operation in each domain. The method allows all of the clock domains, including signal paths which traverse domain boundaries and/or have multi-cycle paths to be tested concurrently and at their respective functional clock rate of each clock.
摘要翻译：一种测试数字系统中的核心逻辑的方法，所述方法具有测试操作的序列，包括测试激励被转移到核心逻辑中的可扫描存储器元件中的移入操作，其中捕获操作捕获存储器元件，并且将捕获的数据从用于分析的核心逻辑中移出的移出操作包括对于每个测试操作，同时使得核心逻辑中的每个时钟域的域时钟的改进每个测试操作的开始，在每个域中执行测试操作，并在每个域中的每个测试操作结束时禁用域时钟。该方法允许所有时钟域，包括跨越域边界的信号路径和/或具有多个循环路径的并行测试并且以其每个时钟的各自的功能时钟速率进行测试。

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