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1. 发明授权

US06327684B1 Method of testing at-speed circuits having asynchronous clocks and controller for use therewith 有权
标题翻译：测试具有异步时钟的高速电路的方法和与其一起使用的控制器
公开(公告)号：US06327684B1
公开(公告)日：2001-12-04
申请号：US09309827
申请日：1999-05-11
申请人： Benoit Nadeau-Dostie , Naader Hasani , Jean-François Coté
发明人： Benoit Nadeau-Dostie , Naader Hasani , Jean-François Coté
IPC分类号： G01R3128
CPC分类号： G01R31/318563 , G01R31/3016 , G01R31/31858 , G01R31/318594
摘要： A method of testing the core logic in a digital system, the method having a sequence of test operations including a shift-in operation in which a test stimulus is shifted into scanable memory elements in the core logic, a capture operation in which data in the memory elements is captured, and a shift-out operation in which captured data is shifted out of the core logic for analysis, comprises the improvement of, for each the test operation, concurrently enabling the domain clock of each clock domain in the core logic at the beginning of each test operation, performing the test operation in each domain and disabling the domain clock at the end of each test operation in each domain. The method allows all of the clock domains, including signal paths which traverse domain boundaries and/or have multi-cycle paths to be tested concurrently and at their respective functional clock rate of each clock.
摘要翻译：一种测试数字系统中的核心逻辑的方法，所述方法具有测试操作的序列，包括测试激励被转移到核心逻辑中的可扫描存储器元件中的移入操作，其中捕获操作捕获存储器元件，并且将捕获的数据从用于分析的核心逻辑中移出的移出操作包括对于每个测试操作，同时使得核心逻辑中的每个时钟域的域时钟的改进每个测试操作的开始，在每个域中执行测试操作，并在每个域中的每个测试操作结束时禁用域时钟。该方法允许所有时钟域，包括跨越域边界的信号路径和/或具有多个循环路径的并行测试并且以其每个时钟的各自的功能时钟速率进行测试。

2. 发明授权

US07757135B2 Method and apparatus for storing and distributing memory repair information 有权
标题翻译：用于存储和分发存储器修复信息的方法和装置
公开(公告)号：US07757135B2
公开(公告)日：2010-07-13
申请号：US11853383
申请日：2007-09-11
申请人： Benoit Nadeau-Dostie , Jean-François Coté
发明人： Benoit Nadeau-Dostie , Jean-François Coté
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/4401 , G11C29/802 , G11C2029/0401 , G11C2029/4402 , G11C2229/726
摘要： A system for repairing embedded memories on an integrated circuit includes an external Built-In Self-repair Register (BISR) associated with every reparable memory. Each BISR is serially configured in a daisy chain with a fuse box controller. The controller determines the daisy chain length upon power up. The controller may perform a corresponding number of shift operations to move repair data between BISRs and a fuse box. Memories can have a parallel or serial repair interface. The BISRs may have a repair analysis facility into which fuse data may be dumped and uploaded to the fuse box or downloaded to repair the memory. Pre-designed circuit blocks provide daisy chain inputs and access ports to effect the system or to bypass the circuit block.
摘要翻译：用于在集成电路上修复嵌入式存储器的系统包括与每个可修复存储器相关联的外部内置自修复寄存器（BISR）。每个BISR以一个带有保险丝盒控制器的菊花链串行配置。控制器在上电时确定菊花链长度。控制器可以执行相应数量的换档操作，以在BISR和保险丝盒之间移动修理数据。存储器可以具有并行或串行修复界面。 BISR可能有一个维修分析设备，熔断器数据可能被转储并上传到保险丝盒或下载以修复存储器。预先设计的电路块提供菊花链输入和访问端口来影响系统或绕过电路块。

3. 发明授权

US08683280B2 Test generator for low power built-in self-test 有权
标题翻译：用于低功率内置自检的发电机
公开(公告)号：US08683280B2
公开(公告)日：2014-03-25
申请号：US13451527
申请日：2012-04-19
申请人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Benoit Nadeau-Dostie
发明人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Benoit Nadeau-Dostie
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318575 , G01R31/31721 , G01R31/318385 , G01R31/3187
摘要： Aspects of the invention relate to low power BIST-based testing. A low power test generator may comprise a pseudo-random pattern generator unit, a toggle control unit configured to generate toggle control data based on bit sequence data generated by the pseudo-random pattern generator unit, and a hold register unit configured to generate low power test pattern data by replacing, based on the toggle control data received from the toggle control unit, data from some or all of outputs of the pseudo-random pattern generator unit with constant values during various time periods. The low power test generator may further comprise a phase shifter configured to combine bits of the low power test pattern data for driving scan chains.
摘要翻译：本发明的方面涉及基于BIST的低功率测试。低功率测试发生器可以包括伪随机模式发生器单元，触发控制单元，被配置为基于由伪随机模式发生器单元生成的比特序列数据产生切换控制数据;以及保持寄存器单元，被配置为产生低功率测试图案数据通过基于从触发控制单元接收到的切换控制数据，在各种时间段期间以常数值替换来自伪随机模式发生器单元的一些或全部输出的数据。低功率测试发生器还可以包括移相器，其被配置为组合用于驱动扫描链的低功率测试图案数据的位。

4. 发明授权

US07257733B2 Memory repair circuit and method 有权
标题翻译：内存修复电路及方法
公开(公告)号：US07257733B2
公开(公告)日：2007-08-14
申请号：US10868208
申请日：2004-06-16
申请人： Benoit Nadeau-Dostie , Saman M. I. Adham
发明人： Benoit Nadeau-Dostie , Saman M. I. Adham
IPC分类号： G06F11/00
CPC分类号： G11C29/846 , G11C29/44 , G11C29/4401 , G11C29/848
摘要： A self-repair circuit for a semiconductor memory provides input and output test selectors coupled to respective data bit group inputs and outputs, respectively and input and output repair selectors coupled between the input and output test selectors and functional inputs and functional outputs, respectively. This arrangement allows all data bit groups to be tested in one pass and all test and repair selector circuitry to be tested.
摘要翻译：用于半导体存储器的自修复电路分别提供耦合到相应数据位组输入和输出的输入和输出测试选择器，以及耦合在输入和输出测试选择器以及功能输入和功能输出之间的输入和输出修复选择器。这种布置允许所有数据位组在一次通过中进行测试，所有测试和修复选择器电路都要进行测试。

5. 发明申请

US20050240848A1 Masking circuit and method of masking corrupted bits 审中-公开
标题翻译：掩蔽电路和掩蔽损坏位的方法
公开(公告)号：US20050240848A1
公开(公告)日：2005-10-27
申请号：US11109844
申请日：2005-04-20
申请人： Jean-Francois Cote , Paul Price , Benoit Nadeau-Dostie
发明人： Jean-Francois Cote , Paul Price , Benoit Nadeau-Dostie
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318572
摘要： A masking circuit for selectively masking scan chain inputs and/or outputs during scan testing of an integrated circuit, comprises a mask register having at least two mask register elements for each scan chain to provide a plurality of masking modes; and an input and output mask control circuit for each scan chain, each mask control circuit being connected between a test pattern source and a signature register and between a serial input and a serial output of an associated scan chain and being responsive to mask control data stored in the register elements for configuring the associated scan chain in one of the plurality of masking modes during a scan test of the circuit.
摘要翻译：一种屏蔽电路，用于在集成电路的扫描测试期间有选择地屏蔽扫描链输入和/或输出，包括屏蔽寄存器，其具有用于每个扫描链的至少两个屏蔽寄存器元件，以提供多个屏蔽模式; 以及用于每个扫描链的输入和输出掩模控制电路，每个掩模控制电路连接在测试图案源和签名寄存器之间，并且连接在相关联的扫描链的串行输入和串行输出之间，并响应于存储的掩码控制数据在用于在电路的扫描测试期间用于将多个掩模模式中的一个掩模模式中的一个配置为关联的扫描链的寄存器元件中。

6. 发明申请

US20050240790A1 Clocking methodology for at-speed testing of scan circuits with synchronous clocks 有权
标题翻译：具有同步时钟的扫描电路的高速测试时钟方法
公开(公告)号：US20050240790A1
公开(公告)日：2005-10-27
申请号：US11060407
申请日：2005-02-18
申请人： Benoit Nadeau-Dostie , Jean-Francois Cote , Fadi Maamari
发明人： Benoit Nadeau-Dostie , Jean-Francois Cote , Fadi Maamari
IPC分类号： G01R31/3185 , G06F13/42
CPC分类号： G01R31/31858
摘要： A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in one of the domains and terminating at a destination memory element in another of the domains and comprises selectively aligning either a capture edge or a launch edge of the clock of each domain with a corresponding edge of at least one other domain of the interacting synchronous clock domains to determine the cross-domain paths to be tested between a source domain and a destination domain; clocking memory elements in each domain at respective domain clock rates to launch signal transitions from source memory elements in source domains; and for each pair of interacting clock domains under test, capturing, in the destination domain, circuit responses to signal transitions launched along paths originating from the source domain and selectively disabling capturing, in the source domain, of circuit responses to signal transitions launched along paths originating from the destination domain.
摘要翻译：一种用于对扫描电路中相互作用的同步时钟域的跨域路径中的延迟缺陷进行高速扫描测试的时钟方法，每个路径源自一个域中的源存储器元件，并终止于另一个的另一个中的目的地存储器元件所述域并且包括选择性地将每个域的时钟的捕获边缘或启动边缘与交互的同步时钟域的至少一个其他域的相应边缘对准，以确定要在源域之间测试的跨域路径和目的域; 以各个域时钟速率在每个域中计时存储器元件以从源域中的源存储器元件启动信号转换; 并且对于正在测试的每对相互作用的时钟域，在目的地域中捕获对源自源域的路径发射的信号转换的电路响应，并且选择性地禁止在源域中捕获沿着路径发射的信号转换的电路响应源自目的地域。

7. 发明授权

US06457161B1 Method and program product for modeling circuits with latch based design 有权
标题翻译：用于基于闩锁设计的电路建模方法和程序产品
公开(公告)号：US06457161B1
公开(公告)日：2002-09-24
申请号：US09817298
申请日：2001-03-27
申请人： Benoit Nadeau-Dostie , Fadi Maamari , Dwayne Burek
发明人： Benoit Nadeau-Dostie , Fadi Maamari , Dwayne Burek
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method of and computer program product for modeling a logic circuit having combinational logic and latches, in which the latches are clocked by one of a first clock phase, a second clock phase or a pulse derived from the second clock phase, a subset of latches being scannable, comprises, for each latch in the logic circuit, associating the latch with one of the first and second clock phase; and when latch is associated with the first clock phase, modeling the latch as a buffer connected between the data input and output of latch; and when the latch is associated with the second clock phase, modeling the latch as an edge-triggered flip-flop having the same data input, data output and clock input as the latch.
摘要翻译：一种用于对具有组合逻辑和锁存器的逻辑电路进行建模的方法和计算机程序产品，其中锁存器由第一时钟相位，第二时钟相位或从第二时钟相位导出的脉冲之一计时，锁存器的子集可扫描的，包括对于逻辑电路中的每个锁存器，将锁存器与第一和第二时钟相位之一相关联; 并且当锁存器与第一时钟相关联时，将锁存器建模为连接在锁存器的数据输入和输出之间的缓冲器; 并且当锁存器与第二时钟相关联时，将锁存器建模为具有与锁存器相同的数据输入，数据输出和时钟输入的边沿触发触发器。

8. 发明授权

US6046946A Method and apparatus for testing multi-port memory using shadow read 失效
标题翻译：使用阴影读取测试多端口存储器的方法和设备
公开(公告)号：US6046946A
公开(公告)日：2000-04-04
申请号：US47233
申请日：1998-03-25
申请人： Benoit Nadeau-Dostie , Jean-Fran.cedilla.ois Cote
发明人： Benoit Nadeau-Dostie , Jean-Fran.cedilla.ois Cote
IPC分类号： G11C8/16 , G11C29/28 , G11C7/00
CPC分类号： G11C29/28 , G11C8/16
摘要： A method of and apparatus for testing multi-port memory performs a shadow read to an adjacent memory cell concurrent with a write operation associated with typical read-write testing. In the presence of a bit wire short or a word wired short, the concurrent read of an adjacent memory cell will cause the value of that cell to be corrupted. The corrupted value is then found by the read-write testing. Consequently, the testing takes no longer than read-write testing. In addition, the testing scheme can be modified for memory with read only ports. An embodiment of the apparatus employs and exclusive OR gate on the least significant bit of the test row address line to generate the shadow read address.
摘要翻译：用于测试多端口存储器的方法和装置对与典型读写测试相关联的写操作同时执行对相邻存储器单元的影子读取。在有线短路或有线短路的情况下，相邻存储单元的并发读取将导致该单元的值被破坏。然后通过读写测试发现损坏的值。因此，测试不再需要读写测试。此外，可以使用只读端口对存储器修改测试方案。该装置的实施例在测试行地址线的最低有效位上采用异或门，以产生影子读取地址。

9. 发明授权

US07188274B2 Memory repair analysis method and circuit 失效
标题翻译：记忆修复分析方法和电路
公开(公告)号：US07188274B2
公开(公告)日：2007-03-06
申请号：US10774512
申请日：2004-02-10
申请人： Benoit Nadeau-Dostie , Robert A. Abbott
发明人： Benoit Nadeau-Dostie , Robert A. Abbott
IPC分类号： G06F11/00
CPC分类号： G11C29/4401 , G11C29/44 , G11C29/72
摘要： A method and circuit for repairing a memory array having one or more memory segments each having one spare column and a predetermined number of spare rows common to all segments, the method comprises, while testing the memory array for failures, generating an equal number of unique segment repair solutions for each segment with each segment repair solution including one defective column address, if any, and a number of defective row addresses, if any, corresponding to the predetermined number of spare rows; and, after completing testing, analyzing all segment repair solution combinations consisting of one segment repair solution selected from each segment; and identifying the best segment repair solution combination of combinations having a number of different defective row addresses which is less than or equal to the predetermined number of spare rows.
摘要翻译：一种用于修复具有一个或多个存储器段的存储器阵列的方法和电路，每个存储器段具有一个备用列和预定数量的所有段公用的备用行，该方法包括在测试存储器阵列以获得故障时产生相等数量的唯一每个段的段修复解决方案，其中每个段修复解决方案包括与预定数量的备用行相对应的一个缺陷列地址（如果有的话）和若干有缺陷的行地址（如果有的话）; 在完成测试后，分析由每个部分选择的一个部分修复解决方案组成的所有段修复解决方案组合; 以及识别具有小于或等于预定数量的备用行的具有多个不同缺陷行地址的组合的最佳段修复方案组合。

10. 发明申请

US20050240847A1 Clock controller for at-speed testing of scan circuits 有权
标题翻译：时钟控制器，用于扫描电路的高速测试
公开(公告)号：US20050240847A1
公开(公告)日：2005-10-27
申请号：US11013319
申请日：2004-12-17
申请人： Benoit Nadeau-Dostie , Jean-Francois Cote
发明人： Benoit Nadeau-Dostie , Jean-Francois Cote
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319
CPC分类号： G01R31/31858 , G01R31/318552 , G01R31/31922
摘要： A test clock controller for generating a test clock signal for scan chains in integrated circuits having one or more clock domains, comprises a shift clock controller for generating a shift clock signal for use in loading test patterns into scan chains in the clock domains and for unloading a test response patterns from the scan chains and for generating a burst phase signal after loading a test pattern; and a burst clock controller associated with each of one or more clock domains and responsive to a burst phase signal for generating a burst of clock pulses derived from a respective reference clocks and including a first group of burst clock pulses having a selected reduced frequency relative to the reference clock and a second group of burst clock pulses having a frequency corresponding to that of the reference clock.
摘要翻译：一种测试时钟控制器，用于在具有一个或多个时钟域的集成电路中产生用于扫描链的测试时钟信号，包括移位时钟控制器，用于产生用于将测试模式加载到时钟域中的扫描链中并用于卸载的移位时钟信号来自扫描链的测试响应模式并且用于在加载测试模式之后产生突发相位信号; 以及突发时钟控制器，其与一个或多个时钟域中的每一个相关联，并且响应于脉冲串相位信号，用于产生从各个参考时钟导出的时钟脉冲串，并且包括相对于相对参考时钟具有选定的降低的频率的第一组脉冲串时钟脉冲参考时钟和具有与参考时钟的频率对应的频率的第二组突发时钟脉冲。

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