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1. 发明授权

US10014847B2 Trigger and oscillation system 有权
公开(公告)号：US10014847B2
公开(公告)日：2018-07-03
申请号：US15654795
申请日：2017-07-20
申请人： SHENZHEN GOODIX TECHNOLOGY CO., LTD.
发明人： Mengwen Zhang
IPC分类号： H03K3/3565 , H03B5/36 , H03K3/012
CPC分类号： H03K3/3565 , H03B5/06 , H03B5/36 , H03B5/362 , H03B5/364 , H03B2200/0012 , H03B2200/0066 , H03B2201/031 , H03K3/012 , H03L3/00
摘要： A trigger, includes: a first voltage input terminal; a bias voltage input terminal; a first bias transistor having a scaling of N to a first component of an external device; a comparator transistor having a scaling of N to a second component of the external device; a first switch transistor and a second switch transistor; a shunt transistor having a control terminal connected to the first voltage input terminal, a second terminal connected to the second terminal of the second switch transistor, and a first terminal connected to the first terminal of the comparator transistor. The shunt transistor has an enlarging scale of M to the comparator transistor. A voltage output terminal is respectively connected to the second terminal of the first switch transistor, the control terminal of the second switch transistor, and the second terminal of the comparator transistor.

2. 发明授权

US09742354B2 Voltage controlled oscillator with common mode adjustment start-up 有权
公开(公告)号：US09742354B2
公开(公告)日：2017-08-22
申请号：US15341352
申请日：2016-11-02
申请人： Microsemi Solutions (U.S.), Inc.
发明人： Hormoz Djahanshahi , Kenneth Allan Townsend
IPC分类号： H03B5/04 , H03B5/06 , H03B5/12 , H03L1/00 , H03L3/00 , H03L5/00 , H03L7/099 , H03K3/03
CPC分类号： H03B5/1293 , H03B5/04 , H03B5/06 , H03B5/1212 , H03B5/1228 , H03B5/1234 , H03B5/124 , H03B5/1278 , H03B5/129 , H03B2200/0094 , H03K3/0315 , H03L1/00 , H03L3/00 , H03L5/00 , H03L7/099
摘要： The present disclosure provides methods and apparatus for dynamically adjusting the common mode voltage at the LC tank node and/or the power supply voltage of a VCO with an LC resonator in order to force oscillation start-up by temporarily increasing gain. Methods according to certain preferred embodiments may reduce power consumption and/or overcome threshold voltage limitations and/or increase frequency and frequency tuning range during normal (steady-state) operation.

3. 发明申请

US20170237441A1 Oscillator Circuit with Bias Current Generator 审中-公开
公开(公告)号：US20170237441A1
公开(公告)日：2017-08-17
申请号：US15314843
申请日：2014-06-02
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： Janne Peltonen , Christian Elgaard , Anna-Karin Stenman
IPC分类号： H03L3/00 , H03B5/32
CPC分类号： H03L3/00 , H03B5/32 , H03B2200/0012 , H03B2200/0062 , H03B2200/0066 , H03B2200/0082 , H03B2200/0094 , H03L5/00
摘要： An oscillator circuit (100) comprises a crystal oscillator (10) arranged to generate an oscillation signal, a bias current generator (20) arranged to supply a bias current to the crystal oscillator (10), and a feedback stage (30) arranged to generate a feedback signal in response to an amplitude of the oscillation signal reaching an amplitude threshold. The bias current generator (20) is arranged to: in response to a supply of power to the oscillator circuit (100) being switched on, generate the bias current at an increasing level commencing from a first level; in response to the feedback signal, terminate the increasing; and during subsequent oscillation of the crystal oscillator (10), supply the bias current at a second level dependent on a final level of the bias current reached when the increasing is terminated.

4. 发明申请

US20170194970A1 CMOS INTERPOLATOR FOR A SERIALIZER/DESERIALIZER COMMUNICATION APPLICATION 有权
公开(公告)号：US20170194970A1
公开(公告)日：2017-07-06
申请号：US15464750
申请日：2017-03-21
申请人： INPHI CORPORATION
发明人： Karthik S. GOPALAKRISHNAN , Guojun REN , Parmanand MISHRA
IPC分类号： H03L7/081 , H04L25/03 , H03L7/08
CPC分类号： H03L7/0812 , H03K5/131 , H03K5/135 , H03K5/14 , H03K2005/00013 , H03K2005/00052 , H03K2005/00286 , H03L3/00 , H03L7/08 , H03L7/0807 , H03L7/0814 , H04L5/0053 , H04L7/002 , H04L7/0331 , H04L25/03273 , H04L27/04
摘要： The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer (SerDes) device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications. In various embodiments, phase-interpolator is implemented in conjunction with a delay-lock loop (DLL) and an SR latch, where one or more outputs of the DLL is used by the SR latch. Additionally, such techniques can be used for a variety of applications such as network and/or computer storage systems, computer servers, hand held computing devices, portable computing devices, computer systems, network appliances and/or switches, routers, and gateways, and the like.

5. 发明授权

US09641313B1 CMOS interpolator for a serializer/deserializer communication application 有权
公开(公告)号：US09641313B1
公开(公告)日：2017-05-02
申请号：US14826051
申请日：2015-08-13
申请人： INPHI CORPORATION
发明人： Karthik S. Gopalakrishnan , Guojun Ren , Parmanand Mishra
IPC分类号： H04L7/00 , H04L7/033 , H03L7/08 , H03K5/14 , H03K5/00
CPC分类号： H03L7/0812 , H03K5/131 , H03K5/135 , H03K5/14 , H03K2005/00013 , H03K2005/00052 , H03K2005/00286 , H03L3/00 , H03L7/08 , H03L7/0807 , H03L7/0814 , H04L5/0053 , H04L7/002 , H04L7/0331 , H04L25/03273 , H04L27/04
摘要： The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer (SerDes) device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications. In various embodiments, phase-interpolator is implemented in conjunction with a delay-lock loop (DLL) and an SR latch, where one or more outputs of the DLL is used by the SR latch. Additionally, such techniques can be used for a variety of applications such as network and/or computer storage systems, computer servers, hand held computing devices, portable computing devices, computer systems, network appliances and/or switches, routers, and gateways, and the like.

6. 发明申请

US20170063387A1 FREQUENCY SYNTHESIZERS WITH ADJUSTABLE DELAYS 有权
标题翻译：具有可调延迟的频率合成器
公开(公告)号：US20170063387A1
公开(公告)日：2017-03-02
申请号：US14836797
申请日：2015-08-26
申请人： NXP B.V.
发明人： Yuan Gao , Frank Leong , Robert Bogdan Staszewski
IPC分类号： H03L7/197 , H03L7/099 , H03K5/13
CPC分类号： H03L7/1974 , H03B5/06 , H03B5/1212 , H03B5/1228 , H03B5/1234 , H03B5/124 , H03B5/1268 , H03K5/131 , H03K2005/00058 , H03L3/00 , H03L5/00 , H03L7/099 , H03L7/0992 , H03L7/18 , H03L2207/06 , H03L2207/50
摘要： A radio frequency (RF) signal can be produced with an RF frequency that is responsive to a frequency reference (FREF) clock. An inductive-capacitive (LC) tank oscillator circuit can generate the RF signal. A digital to time converter (DTC) circuit can operate, for a first edge of the FREF clock, in a baseline mode that has a first delay, and for a subsequent edge of the FREF clock, in a delay mode that introduces a second delay value to the FREF clock. A controller circuit can enable the LC-tank oscillator circuit in response to a first edge of the FREF clock and to set or increase the second delay value of the delay mode as a function of the frequency of the RF signal. A phase detector circuit can detect, for the subsequent edge of the FREF clock, a phase difference between the FREF clock and the RF signal.
摘要翻译：射频（RF）信号可以产生具有响应于频率参考（FREF）时钟的RF频率。电感电容（LC）振荡电路可以产生RF信号。对于FREF时钟的第一边缘，数字到时间转换器（DTC）电路可以在具有第一延迟的基线模式中以及在FREF时钟的后续边沿处以引入第二延迟的延迟模式值到FREF时钟。控制器电路可以响应于FREF时钟的第一边缘而使LC-槽振荡器电路能够设置或增加作为RF信号的频率的函数的延迟模式的第二延迟值。相位检测器电路可以检测FREF时钟的后续边沿FREF时钟和RF信号之间的相位差。

7. 发明申请

US20170054413A1 VOLTAGE CONTROLLED OSCILLATOR WITH COMMON MODE ADJUSTMENT START-UP 有权
标题翻译：电压控制振荡器，具有通用模式调整启动
公开(公告)号：US20170054413A1
公开(公告)日：2017-02-23
申请号：US15341352
申请日：2016-11-02
申请人： Microsemi Storage Solutions (U.S.), Inc.
发明人： Hormoz DJAHANSHAHI , Kenneth Allan TOWNSEND
IPC分类号： H03B5/12 , H03B5/04 , H03L3/00 , H03K3/03
CPC分类号： H03B5/1293 , H03B5/04 , H03B5/06 , H03B5/1212 , H03B5/1228 , H03B5/1234 , H03B5/124 , H03B5/1278 , H03B5/129 , H03B2200/0094 , H03K3/0315 , H03L1/00 , H03L3/00 , H03L5/00 , H03L7/099
摘要： The present disclosure provides methods and apparatus for dynamically adjusting the common mode voltage at the LC tank node and/or the power supply voltage of a VCO with an LC resonator in order to force oscillation start-up by temporarily increasing gain. Methods according to certain preferred embodiments may reduce power consumption and/or overcome threshold voltage limitations and/or increase frequency and frequency tuning range during normal (steady-state) operation.
摘要翻译：本公开提供用于动态地调节LC槽节点处的共模电压和/或具有LC谐振器的VCO的电源电压以便通过暂时增加增益来迫使振荡启动的方法和装置。根据某些优选实施例的方法可以在正常（稳态）操作期间降低功耗和/或克服阈值电压限制和/或增加频率和频率调谐范围。

8. 发明授权

US09571109B2 Voltage controlled oscillator runaway prevention 有权
标题翻译：电压控制振荡器防范
公开(公告)号：US09571109B2
公开(公告)日：2017-02-14
申请号：US14671259
申请日：2015-03-27
申请人： International Business Machines Corporation
发明人： David M. Friend , James D. Strom , Alan P. Wagstaff
IPC分类号： H03L7/06 , H03L7/085 , H03L7/099 , H03L3/00 , H03B5/06 , H03L7/18 , H03L7/22 , H03L7/14 , H03L7/10
CPC分类号： H03L7/085 , H03B5/06 , H03K23/42 , H03L3/00 , H03L7/07 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L7/22 , H03L7/23
摘要： A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.
摘要翻译：用于防止锁相环（PLL）电路中的压控振荡器（VCO）失控的反馈模块可以包括第一，第二和第三输入端，以从PLL电路接收第一输出信号，参考信号和第一控制信号。反馈模块还可以包括用于产生第二控制信号的反馈电路，第二控制信号耦合到PLL电路的输入端，其中反馈电路通过比较第一输出信号的周期数来产生第二控制信号到第一阈值，以及参考信号的周期数到第二阈值。

9. 发明申请

US20160248142A1 RESONANT UNIT, VOLTAGE CONTROLLED OSCILLATOR (VCO) IMPLEMENTING THE SAME, AND PUSH-PUSH OSCILLATOR IMPLEMENTING A PAIR OF VCOS 审中-公开
标题翻译：谐振单元，电压控制振荡器（VCO）实现它们，以及按键振荡器实现一对VCOS
公开(公告)号：US20160248142A1
公开(公告)日：2016-08-25
申请号：US15048427
申请日：2016-02-19
申请人： Sumitomo Electric Industries, Ltd.
发明人： Takeshi Kawasaki , Tsuneo Tokumitsu
IPC分类号： H01P7/02 , H03B7/06 , H03J3/20
CPC分类号： H03B7/06 , H01P5/185 , H03B1/00 , H03B5/18 , H03B5/1847 , H03B5/1852 , H03J3/20 , H03L1/022 , H03L3/00 , H03L5/00 , H03L7/00 , H03L7/06 , H03L7/08 , H03L7/0891 , H03L7/10 , H03L7/18
摘要： A resonant circuit to be connected to a negative resistance unit is disclosed. The resonant circuit includes a pair of resonant transmission lines electrically coupled to each other and a coupling transmission line connecting the resonant transmission lines. The resonant transmission lines and the coupling transmission line are formed on a semiconductor substrate. The resonant transmission lines have a length corresponding to a quarter wavelength (λ/4) of twice of the resonant frequency attributed to the resonant circuit.
摘要翻译：公开了一种连接到负电阻单元的谐振电路。谐振电路包括彼此电耦合的一对谐振传输线和连接谐振传输线的耦合传输线。谐振传输线和耦合传输线形成在半导体衬底上。谐振传输线具有对应于归因于谐振电路的谐振频率的两倍的四分之一波长（λ/ 4）的长度。

10. 发明授权

US09160344B2 Reliable crystal oscillator start-up 有权
标题翻译：可靠的晶体振荡器启动
公开(公告)号：US09160344B2
公开(公告)日：2015-10-13
申请号：US14611112
申请日：2015-01-30
申请人： u-blox AG
发明人： Carmine d'Alessandro
IPC分类号： H03B5/32 , H03L3/00 , H03B5/36
CPC分类号： H03L3/00 , H03B5/32 , H03B5/36 , H03B2200/0082 , H03B2200/0094 , H03L7/099
摘要： The method concerns the reliable start-up of a crystal oscillator where the drive levels the crystal is subjected to are kept low in order to avoid over-driving the crystal. After applying a start-up value of a parameter controlling the drive level where the drive level associated with the start-up value is rather high such that reliable start-up is ensured the parameter is modified step-wise so as to reduce the drive level until the crystal oscillator ceases to operate regularly. To assess whether this is the case, the frequency of the crystal oscillator is compared with the frequency of an auxiliary oscillator. A safety margin is added to the parameter and the result stored in a non-volatile memory as an operating value. The crystal oscillator is then restarted with the start-up value and after a delay the operating value is applied.
摘要翻译：该方法涉及晶体振荡器的可靠启动，其中晶体受到的驱动电平保持较低，以避免过度驱动晶体。在应用控制与启动值相关联的驱动电平相当高的驱动电平的参数的启动值之后，确保可靠的启动，该参数被逐步修改以便降低驱动电平直到晶体振荡器停止定期运行。为了评估是否是这种情况，将晶体振荡器的频率与辅助振荡器的频率进行比较。将安全余量添加到参数中，将结果存储在非易失性存储器中作为运行值。然后以启动值重新启动晶体振荡器，并在延迟后施加工作值。

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