专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

US20240162894A1 Semiconductor Integrated Circuit and Semiconductor Device 审中-公开
公开(公告)号：US20240162894A1
公开(公告)日：2024-05-16
申请号：US18551014
申请日：2021-04-13
申请人： Mitsubishi Electric Corporation
发明人： Osamu NISHIKIDO
IPC分类号： H03K3/356 , H03K3/014 , H03K3/037 , H03K19/173
CPC分类号： H03K3/356043 , H03K3/014 , H03K3/0375 , H03K19/1733
摘要： In a semiconductor integrated circuit, a first analog circuit block operates by a voltage applied between a first node and a third node. Each of a plurality of first current sources has a first end connected to the third node and a second end connected to the first analog circuit block. The plurality of first current sources function as current sourcing or current sinking for the first analog circuit block. A first switch group is provided between the plurality of first current sources and the first analog circuit block, and in a test mode, individually switches electrical connection of the second end of each of the plurality of first current sources from the first analog circuit block to a second node.

2. 发明申请

US20140095757A1 MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP WITH PROGRAMMABLE INTERCONNECT 有权
标题翻译：具有可编程互连的芯片中的微控制器可编程系统
公开(公告)号：US20140095757A1
公开(公告)日：2014-04-03
申请号：US13966028
申请日：2013-08-13
申请人： Cypress Semiconductor Corporation
发明人： Warren S. Snyder
IPC分类号： G06F13/40
CPC分类号： G06F13/4068 , G05B19/0423 , G05B2219/25033 , G06F1/08 , G06F1/32 , G06F9/44505 , G06F13/102 , G06F13/36 , G06F13/40 , G06F13/4282 , G06F15/7817 , G06F15/7867 , G06G7/06 , G11C16/10 , H03B5/32 , H03B5/364 , H03H19/004 , H03K3/012 , H03K3/014 , H03K3/02315
摘要： Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.
摘要翻译：本发明的实施例涉及具有微处理器，可编程存储器组件以及可编程模拟和数字模块的微控制器设备。可编程模拟和数字模块可根据存储在存储器组件中的编程信息进行配置。可编程互连逻辑，也可从存储器组件编程，用于根据需要耦合可编程模拟和数字模块。先进的微控制器设计还包括用于将所选信号耦合到外部引脚的可编程输入/输出块。存储器组件还包括嵌入式微处理器执行的用户程序。这些程序可以包括用于例如动态地对“数字”和“模拟”块进行编程的指令。在一个实现中，存在多个可编程数字块和多个可编程模拟块。

3. 发明授权

US08176296B2 Programmable microcontroller architecture 有权
标题翻译：可编程微控制器架构
公开(公告)号：US08176296B2
公开(公告)日：2012-05-08
申请号：US10033027
申请日：2001-10-22
申请人： Warren Snyder
发明人： Warren Snyder
IPC分类号： G06F15/76
CPC分类号： G06F13/4068 , G05B19/0423 , G05B2219/25033 , G06F1/08 , G06F1/32 , G06F9/44505 , G06F13/102 , G06F13/36 , G06F13/40 , G06F13/4282 , G06F15/7817 , G06F15/7867 , G06G7/06 , G11C16/10 , H03B5/32 , H03B5/364 , H03H19/004 , H03K3/012 , H03K3/014 , H03K3/02315
摘要： Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.
摘要翻译：本发明的实施例涉及具有微处理器，可编程存储器组件以及可编程模拟和数字模块的微控制器设备。可编程模拟和数字模块可根据存储在存储器组件中的编程信息进行配置。可编程互连逻辑，也可从存储器组件编程，用于根据需要耦合可编程模拟和数字模块。先进的微控制器设计还包括用于将所选信号耦合到外部引脚的可编程输入/输出块。存储器组件还包括嵌入式微处理器执行的用户程序。这些程序可以包括用于例如动态地对“数字”和“模拟”块进行编程的指令。在一个实现中，存在多个可编程数字块和多个可编程模拟块。

4. 发明申请

US20120086471A1 PSOC ARCHITECTURE 有权
标题翻译： PSOC架构
公开(公告)号：US20120086471A1
公开(公告)日：2012-04-12
申请号：US13328385
申请日：2011-12-16
申请人： Warren Snyder , Monte Mar
发明人： Warren Snyder , Monte Mar
IPC分类号： H03K19/173
CPC分类号： H03K19/08 , G06F1/08 , G06F1/32 , G06F15/7867 , G06G7/06 , H03B5/364 , H03K3/012 , H03K3/014 , H03K3/02315 , H03K19/173 , H03K19/1733 , H03K19/177 , H03K19/17736 , H03K19/17748
摘要： A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.
摘要翻译：具有多个模拟电路块的电路，每个模拟电路块被配置为提供至少一个模拟功能，以及耦合模拟电路块的可编程互连，并且可配置为将模拟电路块的组合彼此互连。电路形成在集成电路（芯片）中，并且可编程互连包括耦合在模拟电路块和提供芯片的信号连接的端口之间的多个开关。

5. 发明申请

US20110283057A1 Microcontroller Programmable System on a Chip 有权
标题翻译：芯片上的微控制器可编程系统
公开(公告)号：US20110283057A1
公开(公告)日：2011-11-17
申请号：US13169656
申请日：2011-06-27
申请人： Warren Snyder
发明人： Warren Snyder
IPC分类号： G06F12/02
CPC分类号： G06F13/4068 , G05B19/0423 , G05B2219/25033 , G06F1/08 , G06F1/32 , G06F9/44505 , G06F13/102 , G06F13/36 , G06F13/40 , G06F13/4282 , G06F15/7817 , G06F15/7867 , G06G7/06 , G11C16/10 , H03B5/32 , H03B5/364 , H03H19/004 , H03K3/012 , H03K3/014 , H03K3/02315
摘要： Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.
摘要翻译：本发明的实施例涉及具有微处理器，可编程存储器组件以及可编程模拟和数字模块的微控制器设备。可编程模拟和数字模块可根据存储在存储器组件中的编程信息进行配置。可编程互连逻辑，也可从存储器组件编程，用于根据需要耦合可编程模拟和数字模块。先进的微控制器设计还包括用于将所选信号耦合到外部引脚的可编程输入/输出块。存储器组件还包括嵌入式微处理器执行的用户程序。这些程序可以包括用于例如动态地对“数字”和“模拟”块进行编程的指令。在一个实现中，存在多个可编程数字块和多个可编程模拟块。

6. 发明申请

US20060157822A1 Semiconductor integrated circuit having a reduced parasitic capacitance and short start-up time 有权
公开(公告)号：US20060157822A1
公开(公告)日：2006-07-20
申请号：US11330194
申请日：2006-01-12
申请人： Hiroyasu Kunitomo , Tomoaki Nimura , Isamu Kuno , Ryuji Ariyoshi
发明人： Hiroyasu Kunitomo , Tomoaki Nimura , Isamu Kuno , Ryuji Ariyoshi
IPC分类号： H01L29/00
CPC分类号： H01L27/0682 , H01L27/0802 , H01L27/0805 , H03K3/014 , H03K3/0307
摘要： A semiconductor integrated circuit that includes a circuit element with a reduced parasitic capacitance and has a short start-up time. A well of the different type of conduction from that of the substrate is formed in the area of the surface of the semiconductor substrate under the circuit element. A constant voltage, which biases the junction between the well and the semiconductor substrate in a reverse direction, is applied to the well through a resistor having a higher impedance compared with the impedance of the capacitance of the reverse-biased junction between the well and the substrate at the frequency of the signal applied to the circuit element.

7. 发明申请

US20060152291A1 Oscillator circuit, semiconductor device and semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit 有权
公开(公告)号：US20060152291A1
公开(公告)日：2006-07-13
申请号：US11372146
申请日：2006-03-10
申请人： Yasushige Ogawa , Satoru Kawamoto
发明人： Yasushige Ogawa , Satoru Kawamoto
IPC分类号： H03L7/00
CPC分类号： G06F1/04 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/4074 , G11C2207/2227 , G11C2211/4067 , H03K3/012 , H03K3/014 , H03K3/0315 , H03K5/1252 , H03K5/19 , H03L3/00
摘要： There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation- frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value. Thereby, transient state of an oscillation-frequency control signal (VR) can be detected. That is, there can be avoided an output of an unstable oscillation signal due to a transient oscillation-frequency control signal (VR).

8. 发明授权

US06894577B2 Apparatus for providing power control to a real-time clock oscillator 失效
标题翻译：用于向实时时钟振荡器提供功率控制的装置
公开(公告)号：US06894577B2
公开(公告)日：2005-05-17
申请号：US10249737
申请日：2003-05-05
申请人： Mark S. Styduhar
发明人： Mark S. Styduhar
IPC分类号： H03K3/012 , H03K3/014 , H03K3/03 , H03K3/037 , H03L5/00 , H03B5/32
CPC分类号： H03K3/014 , H03B5/06 , H03B5/36 , H03K3/012 , H03K3/0307 , H03K3/0375 , H03L5/00
摘要： An apparatus for providing power control to a real-time clock oscillator is disclosed. The apparatus includes a clock oscillator, a set of current limiting resistors and a set of latches. The current limiting resistors are coupled between a power supply and the clock oscillator. Coupled to the clock oscillator and the current limiting resistors, the latches control the current limiting resistors to limit the amount of current flowing from the power supply to the clock oscillator such that the power consumption by the clock oscillator is minimized.
摘要翻译：公开了一种用于向实时时钟振荡器提供功率控制的装置。该装置包括时钟振荡器，一组限流电阻器和一组锁存器。电流限制电阻耦合在电源和时钟振荡器之间。与时钟振荡器和限流电阻耦合，锁存器控制限流电阻以限制从电源流向时钟振荡器的电流量，使得时钟振荡器的功耗最小化。

9. 发明授权

US06888391B2 Clock generating circuit and clock generating method 失效
标题翻译：时钟发生电路和时钟发生方法
公开(公告)号：US06888391B2
公开(公告)日：2005-05-03
申请号：US10306314
申请日：2002-11-27
申请人： Takahiro Saita
发明人： Takahiro Saita
IPC分类号： G11C5/14 , G06F1/04 , H03B5/32 , H03K3/012 , H03K3/014 , H03K3/02 , H03K3/03 , H03L3/00 , H03K3/00
CPC分类号： G06F1/04 , B60W2520/105 , B60W2520/28 , B60W2530/10 , B60W2530/16 , B60W2550/142 , H03K3/012 , H03K3/014 , H03K3/0307
摘要： A clock generating circuit (100) that may prevent an erroneous clock signal from being provided to an internal logic circuit (105) has been disclosed. A clock generating circuit (100) may include a variable voltage generating circuit (101), an oscillating circuit (103), and a control circuit (104). Oscillating circuit (103) may provide an original clock signal (157). A charging circuit (122, 123, and 124) may provide charging of a signal (159) when an original clock signal (157) achieves a predetermined amplitude. When signal (157) charges sufficiently, an oscillation stabilization signal may be provided to enable the generation of a synthesized clock signal (160). Also, at this time, a reduced voltage (170) may be provided to power an oscillating circuit (103). In this way, current consumption may be reduced and failures due to providing an erroneous clock signal to an internal logic circuit may be reduced.
摘要翻译：已经公开了可以防止错误的时钟信号被提供给内部逻辑电路（105）的时钟发生电路（100）。时钟发生电路（100）可以包括可变电压发生电路（101），振荡电路（103）和控制电路（104）。振荡电路（103）可以提供原始时钟信号（157）。当原始时钟信号（157）达到预定幅度时，充电电路（122,123和124）可以提供信号（159）的充电。当信号（157）充分充电时，可以提供振荡稳定信号以使得能够产生合成时钟信号（160）。此外，此时，可以提供降低的电压（170）来为振荡电路（103）供电。以这种方式，可以减少电流消耗，并且可能减少由于向内部逻辑电路提供错误的时钟信号而导致的故障。

10. 发明申请

US20050046503A1 Oscillator circuit and oscillation stabilizing method 失效
标题翻译：振荡电路和振荡稳定方法
公开(公告)号：US20050046503A1
公开(公告)日：2005-03-03
申请号：US10877987
申请日：2004-06-29
申请人： Yoshimasa Nakahi , Toshifumi Hamaguchi
发明人： Yoshimasa Nakahi , Toshifumi Hamaguchi
IPC分类号： H03B5/32 , H03K3/014 , H03K3/0231 , H03K3/02
CPC分类号： H03K3/02315 , H03B5/364 , H03K3/014
摘要： An oscillator circuit and an oscillation stabilizing method are provided that can improve the productivity of products, stabilize an oscillating operation, and achieve more stable operations for a system supplied with oscillation output. An output from a variable capability oscillator circuit is received by two inverters having different threshold values. Regarding voltage values that are exceeded when oscillation is stabilized in the inverters, the boundaries of the voltage values are set as an astable boundary and an astable boundary which are the threshold values of the inverters, outputs from the inverters are counted by a stable oscillation period shortening circuit based on the timing of a clock used for the system, and the capability of the variable capability oscillator circuit is maximized until oscillation is stabilized, thereby further shortening a stable oscillation period.
摘要翻译：提供振荡电路和振荡稳定方法，其可以提高产品的生产率，稳定振荡操作，并且对于提供有振荡输出的系统实现更稳定的操作。来自可变能力振荡器电路的输出由具有不同阈值的两个反相器接收。关于在逆变器中稳定振荡时超过的电压值，电压值的边界被设定为作为反相器的阈值的不稳定边界和不稳定边界，来自反相器的输出由稳定的振荡周期基于用于系统的时钟的定时的缩短电路，并且可变能量振荡器电路的能力最大化直到振荡稳定，从而进一步缩短稳定的振荡周期。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式