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1. 发明授权

US08977670B2 Processor pipeline which implements fused and unfused multiply-add instructions 有权
标题翻译：处理器管道，其实现融合和未加密的乘法加法指令
公开(公告)号：US08977670B2
公开(公告)日：2015-03-10
申请号：US13469212
申请日：2012-05-11
申请人： Jeffrey S. Brooks , Christopher H. Olson
发明人： Jeffrey S. Brooks , Christopher H. Olson
IPC分类号： G06F7/38 , G06F7/483 , G06F7/544
CPC分类号： G06F7/483 , G06F7/5443 , G06F2207/3884
摘要： Implementing an unfused multiply-add instruction within a fused multiply-add pipeline. The system may include an aligner having an input for receiving an addition term, a multiplier tree having two inputs for receiving a first value and a second value for multiplication, and a first carry save adder (CSA), wherein the first CSA may receive partial products from the multiplier tree and an aligned addition term from the aligner. The system may include a fused/unfused multiply add (FUMA) block which may receive the first partial product, the second partial product, and the aligned addition term, wherein the first partial product and the second partial product are not truncated. The FUMA block may perform an unfused multiply add operation or a fused multiply add operation using the first partial product, the second partial product, and the aligned addition term, e.g., depending on an opcode or mode bit.
摘要翻译：在融合的乘法加法管道中实现未经加密的乘法加法指令。系统可以包括具有用于接收加法项的输入的对准器，具有用于接收第一值的两个输入和用于乘法的第二值的乘法器树，以及第一进位保存加法器（CSA），其中第一CSA可以接收部分乘数树中的乘积和对准器的对齐加法项。该系统可以包括可以接收第一部分乘积，第二部分乘积和对齐的加法项的融合/未融合乘法（FUMA）块，其中第一部分乘积和第二部分乘积不被截断。 FUMA块可以使用第一部分乘积，第二部分积和对齐的相加项来执行未融合的加法运算或融合乘法运算，例如取决于操作码或模式位。

2. 发明申请

US20130179664A1 DIVISION UNIT WITH MULTIPLE DIVIDE ENGINES 有权
标题翻译：具有多个引擎的部门
公开(公告)号：US20130179664A1
公开(公告)日：2013-07-11
申请号：US13345391
申请日：2012-01-06
申请人： Christopher H. Olson , Jeffrey S. Brooks , Matthew B. Smittle
发明人： Christopher H. Olson , Jeffrey S. Brooks , Matthew B. Smittle
IPC分类号： G06F7/487 , G06F9/38 , G06F7/537 , G06F9/302 , G06F5/01 , G06F9/30
CPC分类号： G06F9/3895 , G06F7/49936 , G06F7/535 , G06F7/5375 , G06F9/3001 , G06F9/3875 , G06F9/3885
摘要： Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit.
摘要翻译：公开了涉及包括用于划分和/或平方根操作的硬件支持的集成电路的技术。在一个实施例中，公开了一种集成电路，其包括分割单元，该分割单元又包括归一化电路和多个除法引擎。归一化电路被配置为归一化一组操作数。每个分频引擎被配置为对从归一化电路接收的相应的归一化操作数集进行操作。在一些实施例中，集成电路包括调度器单元，其被配置为选择用于向包括该分割单元的多个执行单元发布的指令。调度器单元还被配置为保持指示当前正在由分割单元操作的指令的数量的计数器，并且基于计数器确定是否计划用于发布到分割单元的后续指令。

3. 发明授权

US07798339B2 Rail and slider system 失效
标题翻译：导轨和滑块系统
公开(公告)号：US07798339B2
公开(公告)日：2010-09-21
申请号：US11668215
申请日：2007-01-29
申请人： Jeffrey S. Brooks , Gregory A. Wirtel
发明人： Jeffrey S. Brooks , Gregory A. Wirtel
IPC分类号： A47H1/00
CPC分类号： G11B33/02
摘要： In general, this invention is directed to a rail and slider system having residential and commercial organizational applications. In one aspect, the system comprises at least one rail and a slider mounted on the rail for sliding movement along the rail. The rail and slider have teeth which releasably engage with one another for locking the slider at selected positions along the rail. A spring device on the slider urges the slider toward a locked position. The slider is manually movable against the urging of the spring device from its locked position to an unlocked position in which the teeth on the arms and the tracks are disengaged to permit sliding movement of the slider along the rail to a different selected position. Various items can be attached to the slider, e.g., a funnel-shaped holder and shelf bracket. In other aspects, the slider is configured for snap-mounting on the rail, and a kit is provided including at least two rails and sliders, and a template for mounting the rails on a surface such that the rails are in proper position relative to one another.
摘要翻译：通常，本发明涉及一种具有住宅和商业组织应用的轨道和滑块系统。在一个方面，该系统包括至少一个轨道和安装在轨道上的滑块，用于沿轨道滑动。轨道和滑块具有可释放地彼此接合的齿，用于将滑块锁定在沿着轨道的选定位置处。滑块上的弹簧装置将滑块推向锁定位置。滑动器可以克服弹簧装置从其锁定位置的推动手动地移动到解锁位置，在该位置，臂和轨道上的齿被分离，以允许滑块沿着轨道滑动到不同的选定位置。可以将各种物品附接到滑块，例如漏斗状保持器和搁架支架。在其它方面，滑动件构造成用于卡扣安装在轨道上，并且提供了包括至少两个轨道和滑块的套件，以及用于将轨道安装在表面上的模板，使得轨道相对于一个位于适当位置另一个。

4. 发明授权

US07774393B1 Apparatus and method for integer to floating-point format conversion 有权
标题翻译：整数到浮点格式转换的装置和方法
公开(公告)号：US07774393B1
公开(公告)日：2010-08-10
申请号：US10881187
申请日：2004-06-30
申请人： Jeffrey S. Brooks , Sadar U. Ahmed
发明人： Jeffrey S. Brooks , Sadar U. Ahmed
IPC分类号： G06F7/00
CPC分类号： H03M7/24
摘要： An apparatus and method for integer to floating-point format conversion. A processor may include an adder configured to perform addition of respective mantissas of two floating-point operands to produce a sum, where a smaller-exponent one of the floating-point operands has a respective exponent less than or equal to a respective exponent of a larger-exponent one of the floating-point operands. The processor may further include an alignment shifter coupled to the adder and configured, in a first mode of operation, to align the floating-point operands prior to the addition by shifting the respective mantissa of the smaller-exponent operand towards a least-significant bit position. The alignment shifter may be further configured, in a second mode of operation, to normalize an integer operand by shifting the integer operand towards a most-significant bit position. The second mode of operation may be active during execution of an instruction to convert the integer operand to floating-point format.
摘要翻译：一种用于整数到浮点格式转换的装置和方法。处理器可以包括加法器，其被配置为执行两个浮点操作数的相应尾数的相加以产生和，其中较小指数的浮点操作数具有小于或等于相应指数的相应指数较大指数的浮点操作数之一。处理器还可以包括对准移位器，其耦合到加法器并且在第一操作模式下被配置为通过将较小指数操作数的相应尾数偏移到最低有效位来对准在加法之前的浮点操作数位置。在第二操作模式中，对准移位器可进一步配置为通过将整数操作数移向最高有效位位置来对整数操作数进行归一化。在执行将整数操作数转换为浮点格式的指令期间，第二操作模式可以是活动的。

5. 发明授权

US06499044B1 Leading zero/one anticipator for floating point 有权
标题翻译：领先的零/一个预期浮点
公开(公告)号：US06499044B1
公开(公告)日：2002-12-24
申请号：US09546412
申请日：2000-04-10
申请人： Jeffrey S. Brooks , James S. Blomgren , David E. Kreml
发明人： Jeffrey S. Brooks , James S. Blomgren , David E. Kreml
IPC分类号： G06F750
CPC分类号： G06F7/74 , G06F7/49 , G06F2207/3832
摘要： An efficient leading zero/leading one anticipator (LZA) that can operate in parallel with a floating point adder is disclosed. In one embodiment, the LZA can be implemented in three levels of N-NARY logic, wherein the first logic level generates dit-level propagate-generate-zero (PGZ) patterns and carry out signals from the input dits of the adder operands. The second logic level produces a find-zero and a find-one output signal for each two-dit group of the adder result by combining PGZ patterns for the two dits within the group with the carry-out signal from the dit immediately preceding the two-dit group. The third logic level combines find-zero and find-one output signals for each two-dit group to produce find-one and find-zero coarse and medium shift select signals.
摘要翻译：公开了一种能够与浮点加法器并行操作的有效率的前导零/前导预测器（LZA）。在一个实施例中，LZA可以在N-NARY逻辑的三个级别中实现，其中第一逻辑电平产生二进制传播生成零（PGZ）模式，并且从加法器操作数的输入位执行信号。第二逻辑电平通过将组内的两个位数的PGZ模式与来自紧接在两者之间的dit的进位信号组合来产生加法器结果的每个二位组的查找零和寻找一个输出信号 -dit组。第三逻辑电平将寻找零和找出一个输出信号组合在一起，以产生找到一个和查找零的粗和中移位选择信号。

6. 发明授权

US6151615A Method and apparatus for formatting an intermediate result for parallel normalization and rounding technique for floating point arithmetic operations 失效
标题翻译：用于格式化用于平移归一化的中间结果和用于浮点运算的舍入技术的方法和装置
公开(公告)号：US6151615A
公开(公告)日：2000-11-21
申请号：US120776
申请日：1998-07-22
申请人： Jeffrey S. Brooks , James S. Blomgren
发明人： Jeffrey S. Brooks , James S. Blomgren
IPC分类号： G06F5/01 , G06F7/57 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49957
摘要： The present invention describes an apparatus and method that formats the output fraction result of an ANSI/IEEE 754-1985 floating point arithmetic operation where parallel normalization and rounding of the intermediate fraction result has occurred. The output fraction is formatted using all or some of the bits from the output of either the rounder circuit or the normalizer circuit.
摘要翻译：本发明描述了一种设备和方法，其格式化ANSI / IEEE 754-1985浮点算术运算的输出分数结果，其中并行归一化和中间分数结果的舍入已经发生。输出分数使用来自四舍五入电路或归一化电路的输出的全部或部分位进行格式化。

7. 发明授权

US06041524A Footwear having recessed heel cup 有权
标题翻译：具有凹陷脚跟杯的鞋类
公开(公告)号：US06041524A
公开(公告)日：2000-03-28
申请号：US166357
申请日：1998-10-05
申请人： Jeffrey S. Brooks
发明人： Jeffrey S. Brooks
IPC分类号： A43B7/16 , A43B13/41 , A43B7/14 , A43B23/28
CPC分类号： A43B7/144 , A43B13/41 , A43B7/16
摘要： Footwear including a sole having a front and a back for supporting a bottom of a foot. A heel cup at the back of the sole receives and supports a heel of the foot. The heel cup has a bottom for further supporting the bottom of the foot and a side wall extending up from the bottom. The side wall has a generally concave rear section for receiving and supporting the back of the heel and opposite side sections extending forward from the rear section. The recess in the rear section of the side wall of the heel cup is offset laterally from a longitudinal central vertical plane of the heel cup. The recess is sized for accommodating the rearwardly protruding lateral posterior portion of the calcaneus of the foot.
摘要翻译：鞋类包括具有用于支撑脚底部的前部和后部的鞋底。在鞋底后部的脚跟接收并支撑足部脚跟。脚跟杯具有用于进一步支撑脚的底部的底部和从底部向上延伸的侧壁。侧壁具有大致凹入的后部，用于接收和支撑后跟的后部和从后部向前延伸的相对侧部。后跟杯的侧壁的后部中的凹部从跟部杯的纵向中心垂直平面侧向偏移。凹部的尺寸适于容纳脚的跟骨的向后突出的侧向后部。

8. 发明授权

US09086890B2 Division unit with normalization circuit and plural divide engines for receiving instructions when divide engine availability is indicated 有权
标题翻译：分配单元具有归一化电路和多个除法引擎，用于在分配发动机可用性时指示
公开(公告)号：US09086890B2
公开(公告)日：2015-07-21
申请号：US13345391
申请日：2012-01-06
申请人： Christopher H. Olson , Jeffrey S. Brooks , Matthew B. Smittle
发明人： Christopher H. Olson , Jeffrey S. Brooks , Matthew B. Smittle
IPC分类号： G06F9/38 , G06F7/535 , G06F7/537 , G06F9/30 , G06F7/499
CPC分类号： G06F9/3895 , G06F7/49936 , G06F7/535 , G06F7/5375 , G06F9/3001 , G06F9/3875 , G06F9/3885
摘要： Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit.
摘要翻译：公开了涉及包括用于划分和/或平方根操作的硬件支持的集成电路的技术。在一个实施例中，公开了一种集成电路，其包括分割单元，该分割单元又包括归一化电路和多个除法引擎。归一化电路被配置为归一化一组操作数。每个分频引擎被配置为对从归一化电路接收的相应的归一化操作数集进行操作。在一些实施例中，集成电路包括调度器单元，其被配置为选择用于向包括该分割单元的多个执行单元发布的指令。调度器单元还被配置为保持指示当前正在由分割单元操作的指令的数量的计数器，并且基于计数器确定是否计划用于发布到分割单元的后续指令。

9. 发明授权

US08458444B2 Apparatus and method for handling dependency conditions between floating-point instructions 有权
标题翻译：用于处理浮点指令之间依赖条件的装置和方法
公开(公告)号：US08458444B2
公开(公告)日：2013-06-04
申请号：US12428459
申请日：2009-04-22
申请人： Yuan C. Chou , Jared C. Smolens , Jeffrey S. Brooks
发明人： Yuan C. Chou , Jared C. Smolens , Jeffrey S. Brooks
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/30032 , G06F9/30109 , G06F9/384 , G06F9/3851 , G06F9/3861
摘要： Techniques for handling dependency conditions, including evil twin conditions, are disclosed herein. An instruction may designate a source register comprising two portions. The source register may be a double-precision register and its two portions may be single-precision portions, each specified as destinations by two other single-precision instructions. Execution of these two single-precision instructions, especially on a register renaming machine, may result in the appropriate values for the two portions of the source register being stored in different physical locations, which can complicate execution of an instruction stream. In response to detecting a potential dependency, one or more instructions may be inserted in an instruction stream to enable the appropriate values to be stored within one physical double precision register, eliminating an actual or potential evil twin dependency. Embodiments including a compiler that inserts instructions in a generated instruction stream to eliminate dependency conditions are also contemplated.
摘要翻译：用于处理依赖条件的技术，包括邪恶的双重条件。指令可以指定包括两个部分的源寄存器。源寄存器可以是双精度寄存器，其两部分可以是单精度部分，每一部分由两个其他单精度指令指定为目标。执行这两个单精度指令，特别是在寄存器重命名机上，可能会导致源寄存器的两个部分的适当值存储在不同的物理位置，这会使指令流的执行变得复杂。响应于检测到潜在依赖性，可以在指令流中插入一个或多个指令，以使适当的值存储在一个物理双精度寄存器中，从而消除实际或潜在的恶性倚靠。包括编译器的实施例也包括在生成的指令流中插入指令以消除依赖条件的编译器。

10. 发明授权

US08452831B2 Apparatus and method for implementing hardware support for denormalized operands for floating-point divide operations 有权
标题翻译：用于实现用于浮点除法运算的非归一化操作数的硬件支持的装置和方法
公开(公告)号：US08452831B2
公开(公告)日：2013-05-28
申请号：US12415370
申请日：2009-03-31
申请人： Christopher H. Olson , Jeffrey S. Brooks
发明人： Christopher H. Olson , Jeffrey S. Brooks
IPC分类号： G06F7/44 , G06F7/487
CPC分类号： G06F7/4873 , G06F7/49915 , G06F7/49936
摘要： A floating-point circuit may include a floating-point operand normalization circuit configured to receive input floating-point operands of a given floating-point divide operation, the operands comprising a dividend and a divisor, as well as a divide engine coupled to the normalization circuit. In response to determining that one or more of the input floating-point operands is a denormal number, the operand normalization circuit may be further configured to normalize the one or more of the input floating-point operands and output a normalized dividend and normalized divisor to the divide engine, and dependent upon respective numbers of leading zeros of the dividend and divisor prior to normalization, generate a value indicative of a maximum possible number of digits of a quotient (NDQ). The divide engine may be configured to iteratively generate NDQ digits of a floating-point quotient from the normalized dividend and the normalized divisor provided by the floating-point operand normalization circuit.
摘要翻译：浮点电路可以包括浮点操作数归一化电路，其被配置为接收给定浮点除法运算的输入浮点操作数，所述操作数包括除数和除数，以及耦合到归一化的除法引擎电路。响应于确定一个或多个输入浮点操作数是反正态数，操作数归一化电路还可以被配置为对输入浮点操作数中的一个或多个进行归一化，并将归一化的除数和归一化除数输出到除法引擎，并且依赖于归一化之前的除数和除数的前导零的相应数量，生成指示商（NDQ）的最大可能数位数的值。划分引擎可以被配置为从浮动点操作数归一化电路提供的归一化除数和归一化除数迭代生成浮点商的NDQ数字。

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