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1. 发明授权

US08498153B2 Semiconductor memory device and method of operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08498153B2
公开(公告)日：2013-07-30
申请号：US13151678
申请日：2011-06-02
申请人： Jin Yong Seong
发明人： Jin Yong Seong
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C2211/5621 , G11C2211/5641
摘要： A semiconductor memory device includes memory blocks each including a plurality of groups of memory cells programmable in multiple levels and a control circuit configured to make a determination of whether a specific memory block treated a bad block, from among the memory blocks, is programmable in a single level and to control the specific memory block according to a result of the determination so that the specific memory block is usable as a single level cell block.
摘要翻译：半导体存储器件包括存储块，每个存储块包括可在多个级别可编程的多组存储器单元;以及控制电路，被配置为确定处理来自存储器块的坏块的特定存储器块是否可编程在并且根据确定的结果来控制特定存储器块，使得特定存储器块可用作单级单元块。

2. 发明授权

US08350374B2 Multi-chip package including chip address circuit 有权
标题翻译：多芯片封装，包括芯片地址电路
公开(公告)号：US08350374B2
公开(公告)日：2013-01-08
申请号：US13151724
申请日：2011-06-02
申请人： Jin Yong Seong
发明人： Jin Yong Seong
IPC分类号： H01L23/02 , H01L23/52 , H01L23/34
CPC分类号： H01L24/06 , G11C5/02 , G11C8/12 , H01L23/50 , H01L24/49 , H01L25/0652 , H01L2224/05554 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01058 , H01L2924/01082 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A multi-chip package according to an aspect of this disclosure includes a plurality of multi-chips. Each of the multi-chips includes a lead configured to receive an external power supply voltage, and a pad circuit configured to reset an internal node to the level of a ground voltage and to generate chip address information by controlling the potential of the internal node based on the state of a connection between the pad circuit and the lead.
摘要翻译：根据本公开的一个方面的多芯片封装包括多个多芯片。每个多芯片包括被配置为接收外部电源电压的引线，以及焊盘电路，其被配置为将内部节点复位到接地电压的电平，并且通过基于内部节点的电位控制来生成芯片地址信息在焊盘电路和引线之间的连接状态。

3. 发明申请

US20120007248A1 MULTI-CHIP PACKAGE INCLUDING CHIP ADDRESS CIRCUIT 有权
标题翻译：多芯片封装，包括芯片地址电路
公开(公告)号：US20120007248A1
公开(公告)日：2012-01-12
申请号：US13151724
申请日：2011-06-02
申请人： Jin Yong SEONG
发明人： Jin Yong SEONG
IPC分类号： H01L23/48
CPC分类号： H01L24/06 , G11C5/02 , G11C8/12 , H01L23/50 , H01L24/49 , H01L25/0652 , H01L2224/05554 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01058 , H01L2924/01082 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A multi-chip package according to an aspect of this disclosure includes a plurality of multi-chips. Each of the multi-chips includes a lead configured to receive an external power supply voltage, and a pad circuit configured to reset an internal node to the level of a ground voltage and to generate chip address information by controlling the potential of the internal node based on the state of a connection between the pad circuit and the lead.
摘要翻译：根据本公开的一个方面的多芯片封装包括多个多芯片。每个多芯片包括被配置为接收外部电源电压的引线，以及焊盘电路，其被配置为将内部节点复位到接地电压的电平，并且通过基于内部节点的电位控制来生成芯片地址信息在焊盘电路和引线之间的连接状态。

4. 发明申请

US20110075479A1 MULTI-LEVEL CELL COPYBACK PROGRAM METHOD IN A NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件中的多级单元复制程序方法
公开(公告)号：US20110075479A1
公开(公告)日：2011-03-31
申请号：US12962570
申请日：2010-12-07
申请人： Jin Yong Seong , Seong Je Park
发明人： Jin Yong Seong , Seong Je Park
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A multi-level cell copyback program method in a non-volatile memory device is disclosed. The method includes performing a multi-level cell copyback program operation; performing selectively a first verifying operation, a second verifying operation or a third verifying operation in accordance with data stored in an MSB node of the first register or data stored in an LSB node of the second register. The first verifying operation is based on a first verifying voltage. The second verifying operation is based on a second verifying voltage higher than the first verifying voltage. And the third verifying operation is based on a third verifying voltage higher than the second verifying voltage. The copy back program operation is performed repeatedly in accordance with result of the verifying operation.
摘要翻译：公开了一种在非易失性存储器件中的多级单元复制程序方法。该方法包括执行多级单元复制程序操作; 根据存储在第一寄存器的MSB节点中的数据或存储在第二寄存器的LSB节点中的数据选择性地执行第一验证操作，第二验证操作或第三验证操作。第一验证操作基于第一验证电压。第二验证操作基于比第一验证电压高的第二验证电压。并且第三验证操作基于比第二验证电压高的第三验证电压。根据验证操作的结果重复执行复制回程序操作。

5. 发明授权

US07660185B2 Chip select controller and non-volatile memory device including the same 有权
标题翻译：芯片选择控制器和非易失性存储器件包括相同的
公开(公告)号：US07660185B2
公开(公告)日：2010-02-09
申请号：US12102705
申请日：2008-04-14
申请人： Jin Yong Seong
发明人： Jin Yong Seong
IPC分类号： G11C8/00
CPC分类号： G11C5/00 , G11C5/143 , G11C8/12
摘要： A chip select controller for a non-volatile memory device includes a first chip enable signal transfer unit, a second chip enable signal transfer unit, a first chip select pad, a second chip select pad, a third chip select pad and a chip select unit. The first chip enable signal transfer unit buffers first and second chip enable signals according to a control signal. The second chip enable signal transfer unit buffers third and fourth chip enable signals according to the control signal. The first chip select pad is configured to transfer a first chip select signal. The second chip select pad is configured to transfer a second chip select signal. The third chip select pad is configured to transfer the second chip select signal. The chip select unit addresses a specific chip according to the first chip select signal and the second chip select signal.
摘要翻译：用于非易失性存储器件的芯片选择控制器包括第一芯片使能信号传送单元，第二芯片使能信号传送单元，第一芯片选择焊盘，第二芯片选择焊盘，第三芯片选择焊盘和芯片选择单元。第一芯片使能信号传送单元根据控制信号缓冲第一和第二芯片使能信号。第二芯片使能信号传送单元根据控制信号缓冲第三和第四芯片使能信号。第一芯片选择板被配置为传送第一芯片选择信号。第二芯片选择焊盘被配置为传送第二芯片选择信号。第三芯片选择板被配置为传送第二芯片选择信号。芯片选择单元根据第一芯片选择信号和第二芯片选择信号寻址特定芯片。

6. 发明申请

US20090287972A1 TEST METHOD FOR NONVOLATILE MEMORY DEVICE 失效
标题翻译：非易失性存储器件的测试方法
公开(公告)号：US20090287972A1
公开(公告)日：2009-11-19
申请号：US12362441
申请日：2009-01-29
申请人： Wan Seob LEE , Jin Yong Seong
发明人： Wan Seob LEE , Jin Yong Seong
IPC分类号： G11C29/10 , G06F11/263
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/56012 , G11C2029/2602 , G11C2029/5602
摘要： A test method for nonvolatile memory devices where, in one aspect of the method, a specific operation mode is selected according to a signal input through a single I/O pin in a period in which a write enable signal is inactivated. The write enable signal or a read enable signal is activated according to the selected operation mode. A plurality of signals is input through the single I/O pin in a period in which the write enable signal is activated. The plurality of signals is output through the single I/O pin in a period in which the read enable signal is activated.
摘要翻译：一种用于非易失性存储器件的测试方法，其中在该方法的一个方面中，根据在写入使能信号被禁止的时段中通过单个I / O引脚输入的信号来选择特定操作模式。写使能信号或读使能信号根据所选择的操作模式被激活。在写使能信号被激活的时间段内，通过单个I / O引脚输入多个信号。在读使能信号被激活的时间段内，多个信号通过单个I / O引脚输出。

7. 发明授权

US07508709B2 Page buffer circuit with reduced size and methods for reading and programming data with the same 有权
标题翻译：具有减小尺寸的页面缓冲电路和用于读取和编程数据的方法
公开(公告)号：US07508709B2
公开(公告)日：2009-03-24
申请号：US11304526
申请日：2005-12-14
申请人： Jin Yong Seong , Sam Kyu Won
发明人： Jin Yong Seong , Sam Kyu Won
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C16/3459 , G11C2211/5642
摘要： A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation.
摘要翻译：提供了一种缩小尺寸的页面缓冲电路和用于读取和编程数据的方法。在读取操作中，页缓冲器电路通过交替地使用较高位寄存器或低位寄存器读出数据位，而不管从多级单元读取的数据位是高位还是低位，从而减少电路面积提高了运行性能。

8. 发明授权

US07333365B2 Page buffer of flash memory device with improved program operation performance and program operation control method 有权
标题翻译：闪存器件的页面缓冲器，具有改进的编程操作性能和程序操作控制方法
公开(公告)号：US07333365B2
公开(公告)日：2008-02-19
申请号：US11298178
申请日：2005-12-08
申请人： Jin Yong Seong
发明人： Jin Yong Seong
IPC分类号： G11C11/34
CPC分类号： G11C11/5628
摘要： TA page buffer of a flash memory device has a page buffer that improves the program operation performance and program operation control method thereof. The page buffer has a flash memory device having a MLC. The page buffer stores input data in an upper bit register, initial data having the same value as that of the input that data are stored in a lower bit register.
摘要翻译：闪速存储器件的TA页缓冲器具有提高程序运行性能的页缓冲器及其程序运算控制方法。页面缓冲器具有具有MLC的闪存器件。页面缓冲器将输入数据存储在高位寄存器中，初始数据具有与数据存储在低位寄存器中的输入值相同的值。

9. 发明授权

US08125828B2 Page buffer circuit with reduced size and methods for reading and programming data with the same 有权
标题翻译：具有减小尺寸的页面缓冲电路和用于读取和编程数据的方法
公开(公告)号：US08125828B2
公开(公告)日：2012-02-28
申请号：US12409400
申请日：2009-03-23
申请人： Jin Yong Seong , Sam Kyu Won
发明人： Jin Yong Seong , Sam Kyu Won
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C16/3459 , G11C2211/5642
摘要： A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation.
摘要翻译：提供了一种缩小尺寸的页面缓冲电路和用于读取和编程数据的方法。在读取操作中，页缓冲器电路通过交替地使用较高位寄存器或低位寄存器读出数据位，而不管从多级单元读取的数据位是高位还是低位，从而减少电路面积提高了运行性能。

10. 发明申请

US20120008390A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20120008390A1
公开(公告)日：2012-01-12
申请号：US13151678
申请日：2011-06-02
申请人： Jin Yong SEONG
发明人： Jin Yong SEONG
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C2211/5621 , G11C2211/5641
摘要： A semiconductor memory device includes memory blocks each including a plurality of groups of memory cells programmable in multiple levels and a control circuit configured to make a determination of whether a specific memory block treated a bad block, from among the memory blocks, is programmable in a single level and to control the specific memory block according to a result of the determination so that the specific memory block is usable as a single level cell block.
摘要翻译：半导体存储器件包括存储块，每个存储块包括可在多个级别可编程的多组存储器单元;以及控制电路，被配置为确定处理来自存储器块的坏块的特定存储器块是否可编程在并且根据确定的结果来控制特定存储器块，使得特定存储器块可用作单级单元块。

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