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1. 发明授权

US06651021B2 System using adaptive circuitry to improve performance and provide linearity and dynamic range on demand 有权
公开(公告)号：US06651021B2
公开(公告)日：2003-11-18
申请号：US09881932
申请日：2001-06-15
申请人： Paul A. Underbrink , Daryush Shamlou , Ricke W. Clark , Joseph H. Colles , Guangming Yin , Patrick D. Ryan , Kelly H. Hale
发明人： Paul A. Underbrink , Daryush Shamlou , Ricke W. Clark , Joseph H. Colles , Guangming Yin , Patrick D. Ryan , Kelly H. Hale
IPC分类号： G01R3500
CPC分类号： H04B1/109
摘要： The invention discloses a system for improving performance of the RF amplification stage of communication receivers by accounting for the signal environment of the RF amplifier. The linearity, gain and power supply voltage of the RF amplification stage of the communication receiver is adjusted to produce an optimal signal into the succeeding narrow-band amplification stage(s). The adjustment of the RF stage includes mechanisms such as adjusting the RF amplifier power supply level using a DC to DC converter. It also includes allowing distortion in the RF amplification stage if the distortion in the RF amplification stage does not affect the target signal. For example, if there were a strong signal that fell within the same band as the target signal, amplification would be allowed to be so high that it distorted the undesired signals, but not the tined signals. If the desired signal is the predominant signal, within the RF amplifier's band, then the amplifier gain may be increased only to the point where distortion is detected.

2. 发明授权

US5198703A System for detecting voltage pulses of a particular magnitude 失效
标题翻译：用于检测特定大小的电压脉冲的系统
公开(公告)号：US5198703A
公开(公告)日：1993-03-30
申请号：US802072
申请日：1991-12-03
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： B60T8/48 , G01R19/165
CPC分类号： B60T8/4827 , G01R19/16585
摘要： First circuitry on an integrated circuit chip has an input terminal, preferably the only input terminal, for receiving a voltage pulse introduced to a first terminal on the chip. The first circuitry damps the negative voltage peaks of the voltage pulse at a voltage of a first magnitude inherent in the construction of the first circuitry. A pair of input transistors in the first circuitry have dimensions to provide, at the input terminal to second circuitry, a clamping voltage of a first magnitude at a certain fraction of the power supply voltage. The first circuitry may include a closed loop servo amplifier which regulates the negative peaks of the pulse at the input terminal to the second circuitry to a value approximately equal to the voltage of the first magnitude. The second circuitry compares the negative peaks of the input voltage pulse with a voltage of a second magnitude inherent in the construction of the second circuitry to provide an output logic pulse. A pair of input transistors in the second circuitry have dimensions to provide an internal reference voltage of the second magnitude. Differences between the dimensions of the input transistors in the second circuitry and the first circuitry provide a slight but accurate difference between the voltages of second and first magnitudes. The output pulse may constitute a horizontal sync pulse having amplitude not slightly more negative than the negative peaks of a color burst following it. This pulse provides for a faithful reproduction of color from color information signals following the color burst signals.
摘要翻译：集成电路芯片上的第一电路具有用于接收引入到芯片上的第一端子的电压脉冲的输入端子，最好是唯一的输入端子。第一电路将电压脉冲的负电压峰值减去第一电路结构固有的第一幅度的电压。第一电路中的一对输入晶体管具有在电源电压的一定分数下在第二电路的输入端提供第一幅度的钳位电压的尺寸。第一电路可以包括闭环伺服放大器，其将在第二电路的输入端处的脉冲的负峰值调节到大致等于第一幅度的电压的值。第二电路将输入电压脉冲的负峰值与在第二电路结构中固有的第二幅度的电压进行比较以提供输出逻辑脉冲。第二电路中的一对输入晶体管具有提供第二幅度的内部参考电压的尺寸。第二电路和第一电路中的输入晶体管的尺寸之间的差异提供了第二和第一幅度的电压之间的轻微但精确的差异。输出脉冲可以构成水平同步脉冲，该水平同步脉冲的幅度不比其随后的色同步脉冲的负峰值稍微大一些。该脉冲提供了在色同步信号之后的颜色信息信号的忠实再现。

3. 发明授权

US5150077A Generation of horizontal sync pulse 失效
标题翻译：生成水平同步脉冲
公开(公告)号：US5150077A
公开(公告)日：1992-09-22
申请号：US766817
申请日：1991-09-26
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： H04N5/10 , H04N5/12
CPC分类号： H04N5/126
摘要： A system eliminates the adverse effects of serration and equalization pulses (periodically generated during the vertical sync interval) in regulating the frequency of horizontal sync pulses. These sync pulses provide timing information to regulate a video display. The system includes circuitry for stripping and processing the horizontal and vertical sync signals and the serration pulses from the video signals. These pulses are introduced to a first AND gate and through a first display line to an input of a second AND gate. Frequency divider output signals are introduced to the first AND gate and to a third AND gate through a second delay line having an equal delay with the first delay line. The output from the first AND gate passes to second inputs of the second and third AND gates. The second and third AND gates produce signals which represent the time difference between the sync and divider output signals and which have a maximum time difference equal to the delays of the delay lines. In doing so, the gates eliminate the effects of the serration and equalization pulses. A phase comparator compares the times of occurrence of the second and third AND gate signals and introduces to a low pass filter and signals representing the time difference. A voltage controlled oscillator produces a signal having a frequency dependent upon the magnitude of the output voltage from the filter. The frequency of the oscillator signals is passed to a frequency divider. The resultant divider signals are introduced to the first AND gate and the second delay line.

4. 发明授权

US07072698B2 Directional antenna for hand-held wireless communications device 有权
标题翻译：手持无线通信设备的定向天线
公开(公告)号：US07072698B2
公开(公告)日：2006-07-04
申请号：US09394189
申请日：1999-09-13
申请人： Paul A. Underbrink , Kelly H. Hale , Guang-Ming Yin , Patrick D. Ryan , Joseph H. Colles , Daryush Shamlou , Christian Levesque
发明人： Paul A. Underbrink , Kelly H. Hale , Guang-Ming Yin , Patrick D. Ryan , Joseph H. Colles , Daryush Shamlou , Christian Levesque
IPC分类号： H04M1/00
CPC分类号： H01Q9/0407 , H01Q1/245 , H01Q1/246 , H04W88/02
摘要： A system for wireless communications is provided. The system includes a hand-held wireless communications device, such as a cell phone. An antenna is connected to the cell phone. The antenna radiates radio waves over an area of less than 360 degrees of arc, such as in a cardioid or hemisphere. The antenna is oriented such that hemisphere is in the direction away from a head of a user of the cell phone.
摘要翻译：提供了一种用于无线通信的系统。该系统包括诸如手机的手持式无线通信设备。天线连接到手机。天线辐射无线电波在小于360度弧度的区域，例如在心形或半球中。天线被定向成使得半球在离开手机的用户的头部的方向上。

5. 发明授权

US06933876B1 Pipelined analog to digital converter 有权
标题翻译：流水线模数转换器
公开(公告)号：US06933876B1
公开(公告)日：2005-08-23
申请号：US10104381
申请日：2002-03-22
申请人： Paul A. Underbrink , Kelly H. Hale , Guang-Ming Yin , Patrick D. Ryan , Joseph H. Colles , Daryush Shamlou
发明人： Paul A. Underbrink , Kelly H. Hale , Guang-Ming Yin , Patrick D. Ryan , Joseph H. Colles , Daryush Shamlou
IPC分类号： H03M1/00 , H03M1/44 , H04B1/00 , H04B1/40 , H04M1/00 , H04W88/06
CPC分类号： H03M1/004 , H03M1/007 , H03M1/44 , H04B1/406 , H04W88/06
摘要： A cell phone is provided that may be used with multiple radio formats, such as GSM and CDMA. The cell phone includes a receiver that receives radio signals and converts them into electrical signals. An analog to digital converter is connected to the receiver and converts an analog input to a digital output having an adjustable number of bits at an adjustable sampling frequency. A cell phone application specific integrated circuit is connected to the analog to digital converter, which is used to process the digital output to extract encoded telecommunications data in one of the supported radio formats.
摘要翻译：提供了可以与诸如GSM和CDMA之类的多种无线电格式一起使用的手机。手机包括接收无线电信号并将其转换成电信号的接收机。模拟数字转换器连接到接收器，并将模拟输入转换成具有可调节采样频率的可调节位数的数字输出。手机应用专用集成电路连接到模拟数字转换器，用于处理数字输出以以支持的无线电格式之一提取编码的电信数据。

6. 发明授权

US4904922A Apparatus for converting between digital and analog values 失效
标题翻译：用于在数字和模拟值之间转换的装置
公开(公告)号：US4904922A
公开(公告)日：1990-02-27
申请号：US225055
申请日：1988-07-26
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： H03M1/68 , H03M1/74
CPC分类号： H03M1/685 , H03M1/747
摘要： Output members in a matrix relationship having x and y inputs respectively receive signals in first and second pluralities cumulatively representing a digital value. These signals are decoded and are respectively introduced to the x and y inputs to activate a particular output member common to a selected x row and a selected y column. The output members in the preceding rows and preceding the activated output member in the selected row are also activated. Three-transistor (all of the same type) current sources provide constant currents to the activated output members. In each current source, a first transistor provides the constant current, a second transistor in each current source constitutes a switch operative in response to binary input signals, and a third transistor receives the constant current dependent upon the binary input to the second transistor. A circuit providing first and second reference voltages and including an operational amplifier produces a resultant voltage representing the difference between the reference voltages. The resultant voltage controls the current flowing through fourth and fifth transistors, preferably in series, thereby regulating the value of the first reference voltage. The amplifier output also regulates the current in the first transistor of each current cell, and the voltage from the fifth transistor biases the third transistor in each current cell toward a conductive state. The three transistors in each current source and the fourth and fifth transistors may be C-MOS transistors of the p type.
摘要翻译：具有x和y输入的矩阵关系的输出成员分别以第一和第二多个累积地表示数字值的信号接收信号。这些信号被解码并分别被引入x和y输入以激活所选x行和所选择的y列共有的特定输出成员。前一行中的输出成员和所选行中激活的输出成员之前的激活。三晶体管（所有相同类型）电流源为激活的输出元件提供恒定电流。在每个电流源中，第一晶体管提供恒定电流，每个电流源中的第二晶体管构成响应于二进制输入信号而工作的开关，并且第三晶体管根据二阶输入到第二晶体管接收恒定电流。提供第一和第二参考电压并且包括运算放大器的电路产生表示参考电压之间的差的合成电压。所得到的电压控制流过第四和第五晶体管的电流，优选地串联，从而调节第一参考电压的值。放大器输出还调节每个电流单元的第一晶体管中的电流，并且来自第五晶体管的电压将每个当前单元中的第三晶体管偏置为导通状态。每个电流源中的三个晶体管和第四和第五晶体管可以是p型的C-MOS晶体管。

7. 发明授权

US4899151A Apparatus for converting digital values to analog values 失效
标题翻译：用于将数字值转换为模拟值的装置
公开(公告)号：US4899151A
公开(公告)日：1990-02-06
申请号：US915784
申请日：1986-10-06
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： H03M1/74 , H03M1/00
CPC分类号： H03M1/687 , H03M1/685
摘要： A plurality of members, each constructed to produce a substantially constant current when energized, are disposed electrically in a matrix defined by a plurality of rows and a plurality of columns. A plurality of signals cumulatively represent a digital value. Each of the signals has logic levels respectively coding for binary "1" and binary "0" and each has an individual binary significance. The binary signals of intermediate binary significance are decoded to activate an individual rows. The binary signals of high binary significance are decoded to activate an individual column. The member common to the activated row and the activated column then receives a substantially constant current, as do all of the members of lower binary signficance than such common member. The signals of lowest binary significance are also decoded to produce a current having a magnitude indicative of the binary value coded by such signals. This magnitude corresponds to that obtained by multiplying a particular portion of the substantially constant current by a ratio having as a numerator the value represented by the binary signals of least binary significance and having as its denominator the maximum value capable of being coded by such binary signals. The current coding for the binary signals of the least binary significance passes through a member otherwise superfluous in the matrix and preferably having an extreme position electrically in the matrix. The currents flowing through the members in the matrix are added in an output line to indicate an analog of the digital value.
摘要翻译：被构造成在通电时产生基本上恒定的电流的多个构件电气地设置在由多个行和多个列限定的矩阵中。多个信号累积地表示数字值。每个信号具有分别编码二进制“1”和二进制“0”的逻辑电平，并且每个具有单独的二进制含义。中间二进制有效的二进制信号被解码以激活单独的行。高二进制有效的二进制信号被解码以激活单独的列。所激活的行和激活的列共同的成员然后接收基本上恒定的电流，与所有这些公共成员相比较低的二进制值的所有成员也是如此。最低二进制有效性的信号也被解码以产生具有表示由这些信号编码的二进制值的幅度的电流。该幅度对应于通过将基本上恒定的电流的特定部分乘以具有由最小二进制有效值的二进制信号表示的值作为分子而具有作为其分母的能够由这种二进制信号编码的最大值的比例而获得的量值。对二进制有意义的二进制信号的当前编码通过在矩阵中多余的成员，优选地在矩阵中具有极端位置。流过矩阵中的构件的电流被添加到输出线中以指示数字值的模拟。

8. 发明授权

US4638241A Regulated current supply 失效
标题翻译：调节电流供应
公开(公告)号：US4638241A
公开(公告)日：1987-01-20
申请号：US775524
申请日：1985-09-13
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： G05F3/24 , H03M1/00 , G05F3/08
CPC分类号： G05F3/247 , H03M1/124
摘要： A first semi-conductor has a first threshold voltage and provides a particular voltage drop across it in its saturated state of operation. A second semi-conductor has a second threshold voltage and provides the particular voltage drop across it in its saturated state of operation. The second semi-conductor may be a native device. The first and second semi-conductors are connected to provide a common flow of current. A current is induced, as by a third semi-conductor, to flow in the second semi-conductor. The first and second semi-conductors are commonly biased to produce a flow of saturated current through them when a current is induced to flow in the second semi-conductor. Each of the first, second and third semi-conductors may be provided with a gate, drain and source. The sources and drains of the semi-conductors may be in series. The gates of the first and second semi-conductors may be commonly biased and the gate of the third semi-conductor may be biased to produce the flow of current through the second and third semi-conductors. A circuit may be connected across the first semi-conductor and may be provided with first and second states of operation. In the first state, the saturated current flows through the third, second and first semi-conductors and, in the second state, the saturated current flows through the third and second semi-conductors and the parallel circuit. The parallel circuit may be included in a digital-to-analog converter in which bits are disposed in rows and columns and in which an analog value is produced by activating bits in selected rows and columns.
摘要翻译：第一半导体具有第一阈值电压并且在其饱和的操作状态下在其上提供特定的电压降。第二半导体具有第二阈值电压，并且在其饱和的操作状态下提供跨越其的特定电压降。第二半导体可以是本地设备。连接第一和第二半导体以提供公共的电流。由第三半导体引起电流在第二半导体中流动。当电流在第二半导体中流动时，第一和第二半导体通常被偏置以产生通过它们的饱和电流。第一，第二和第三半导体中的每一个可以设置有栅极，漏极和源极。半导体的源极和漏极可以是串联的。第一和第二半导体的栅极可以被公共偏置，并且第三半导体的栅极可被偏置以产生通过第二和第三半导体的电流。电路可以跨越第一半导体连接并且可以被提供有第一和第二操作状态。在第一状态下，饱和电流流过第三，第二和第一半导体，并且在第二状态下，饱和电流流过第三和第二半导体和并联电路。并行电路可以包括在数模转换器中，其中位以行和列布置，并且其中通过激活所选行和列中的位产生模拟值。

9. 发明授权

US4298888A Non-interlaced to interlaced format video converter 失效
标题翻译：非隔行扫描格式的视频转换器
公开(公告)号：US4298888A
公开(公告)日：1981-11-03
申请号：US46745
申请日：1979-06-08
申请人： Joseph H. Colles , James E. Cooper, Jr.
发明人： Joseph H. Colles , James E. Cooper, Jr.
IPC分类号： H04N5/44 , H04N7/01 , H04N5/02
CPC分类号： H04N7/012 , H04N7/0105
摘要： A video converter operating in real time that responds to frames of N lines of video data in a non-interlaced format to form two fields of interlaced data without loss of any information. The converter operates with a minimum of two lines of memory storage capacity and a minimum of timing structure. The concept in accordance with the invention allows data of substantially any non-interlaced format to be converted for display on an interlaced display unit such as a standard TV system.
摘要翻译：一种实时操作的视频转换器，以非隔行格式响应N行视频数据的帧，以形成两个隔行扫描数据，而不会丢失任何信息。该转换器以至少两行存储容量和最小时序结构运行。根据本发明的概念允许基本上任何非隔行扫描格式的数据被转换以在诸如标准TV系统的隔行显示单元上显示。

10. 发明授权

US08351880B1 Saturation corrected power amplifier integration loop 有权
标题翻译：饱和校正功率放大器集成环路
公开(公告)号：US08351880B1
公开(公告)日：2013-01-08
申请号：US12841712
申请日：2010-07-22
申请人： Alexander W. Hietala , Joseph H. Colles
发明人： Alexander W. Hietala , Joseph H. Colles
IPC分类号： H01Q11/12 , H04B1/04
CPC分类号： H03F3/245 , H03G3/3047
摘要： Embodiments of the present disclosure relate to an radio frequency (RF) power amplifier (PA) module having a saturation corrected integration loop, which includes saturation detection and correction circuitry, an integrator, PA circuitry, and detector circuitry. An integrator output signal from the integrator is prevented from being driven toward a power supply rail in the presence of saturation of the PA circuitry by saturation correction of an input ramp signal. The saturation detection and correction circuitry receives and saturation corrects the input ramp signal to provide a saturation corrected input ramp signal to the integrator based on detecting saturation of the PA circuitry. Saturation of the PA circuitry is detected based on a difference between a desired PA output voltage, as indicated by the input ramp signal, and a detected PA output voltage, as indicated by a detector output signal from the detector circuitry.
摘要翻译：本公开的实施例涉及具有饱和校正积分环路的射频（RF）功率放大器（PA）模块，其包括饱和检测和校正电路，积分器，PA电路和检测器电路。在积分器的积分器输出信号通过输入斜坡信号的饱和校正在PA电路饱和的情况下，不会被驱动朝向电源轨。饱和检测和校正电路接收并饱和校正输入斜坡信号，以基于检测PA电路的饱和度向积分器提供饱和校正的输入斜坡信号。基于由输入斜坡信号指示的期望的PA输出电压和检测到的PA输出电压之间的差异检测PA电路的饱和度，如来自检测器电路的检测器输出信号所示。

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