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1. 发明申请

US20230130656A1 System and platform for enabling personal health data ownership 有权
公开(公告)号：US20230130656A1
公开(公告)日：2023-04-27
申请号：US17975246
申请日：2022-10-27
申请人： Jun Beom Park , Vinay Manjunath Pai , Dhruv Bhandarkar Pai , John Paul Metzcar
发明人： Jun Beom Park , Vinay Manjunath Pai , Dhruv Bhandarkar Pai , John Paul Metzcar
IPC分类号： G06F21/62
摘要： A system is disclosed for a platform that enables the biological owner of health data to manage and control access to their health data. In an embodiment, biological owners can take possession of their own health data. They control the level of access to their own health data by third parties through the use of data blurring to fit within specific data ranges. They also control access to their data through data encryption. In another embodiment, the biological owner of the health data can provide access to their health data to third parties through an auction system. Such access would be provided based on price, time duration of access, or quality of data, as determined by the biological owner of the health data. Additionally, such access could be provided by the system managing the health data access for the biological owner of the health data.

2. 发明申请

US20080272434A1 NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080272434A1
公开(公告)日：2008-11-06
申请号：US11876638
申请日：2007-10-22
申请人： Jun-Beom PARK , Ki-Nam KIM , Soon-Moon JUNG , Jae-Hoon JANG
发明人： Jun-Beom PARK , Ki-Nam KIM , Soon-Moon JUNG , Jae-Hoon JANG
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/115 , H01L27/0688 , H01L27/11521 , H01L27/11551
摘要： A non-volatile memory device and a method of manufacturing the same are disclosed. In the non-volatile memory device, first gate structures and first impurity diffusion regions are formed on a substrate. A first insulating interlayer is formed on the substrate. A semiconductor layer including second gate structures and second impurity diffusion regions is formed on the first insulating interlayer. A second insulating interlayer is formed on the semiconductor layer. A contact plug connecting the first impurity diffusion regions to the second impurity diffusion regions is formed. A common source line connected to the contact plug is formed on the second insulating interlayer. The common source line connected to the first and second impurity diffusion regions is formed over a top semiconductor layer.
摘要翻译：公开了一种非易失性存储器件及其制造方法。在非易失性存储器件中，在衬底上形成第一栅极结构和第一杂质扩散区。在基板上形成第一绝缘中间层。在第一绝缘中间层上形成包括第二栅极结构和第二杂质扩散区的半导体层。在半导体层上形成第二绝缘中间层。形成将第一杂质扩散区域连接到第二杂质扩散区域的接触插塞。在第二绝缘中间层上形成连接到接触塞的共同源极线。连接到第一和第二杂质扩散区的公共源极线形成在顶部半导体层上。

3. 发明授权

US07646664B2 Semiconductor device with three-dimensional array structure 有权
标题翻译：具有三维阵列结构的半导体器件
公开(公告)号：US07646664B2
公开(公告)日：2010-01-12
申请号：US11869140
申请日：2007-10-09
申请人： Hoo-Sung Cho , Soon-Moon Jung , Young-Seop Rah , Jae-Hoon Jang , Jae-Hun Jeong , Jun-Beom Park
发明人： Hoo-Sung Cho , Soon-Moon Jung , Young-Seop Rah , Jae-Hoon Jang , Jae-Hun Jeong , Jun-Beom Park
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/08 , G11C8/14 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11568
摘要： A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.
摘要翻译：一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线，并且第一字线可以在第一和第二半导体层之间。第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。

4. 发明申请

US20090251962A1 Three-Dimensional Memory Device and Driving Method Thereof 失效
标题翻译：三维存储器件及其驱动方法
公开(公告)号：US20090251962A1
公开(公告)日：2009-10-08
申请号：US12418821
申请日：2009-04-06
申请人： Jong-In Yun , Jae-Hoon Jang , Soon-Moon Jung , Han-Soo Kim , Jun-Beom Park , Jae-Hun Jeong
发明人： Jong-In Yun , Jae-Hoon Jang , Soon-Moon Jung , Han-Soo Kim , Jun-Beom Park , Jae-Hun Jeong
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G11C16/3418 , G11C16/3427 , H01L27/11551
摘要： A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A well of an unselected layer is biased with a second well voltage higher than the first well voltage.
摘要翻译：提供具有多个层的三维存储器件的驱动方法。选择其中一个图层。所选择的层的阱被第一阱电压偏置。字线电压被施加到所选层的选定字线。未选择的层的阱以比第一阱电压高的第二阱电压偏置。

5. 发明申请

US20080084729A1 SEMICONDUCTOR DEVICE WITH THREE-DIMENSIONAL ARRAY STRUCTURE 有权
标题翻译：具有三维阵列结构的半导体器件
公开(公告)号：US20080084729A1
公开(公告)日：2008-04-10
申请号：US11869140
申请日：2007-10-09
申请人： Hoo-Sung Cho , Soon-Moon Jung , Young-Seop Rah , Jae-Hoon Jang , Jae-Hun Jeong , Jun-Beom Park
发明人： Hoo-Sung Cho , Soon-Moon Jung , Young-Seop Rah , Jae-Hoon Jang , Jae-Hun Jeong , Jun-Beom Park
IPC分类号： G11C5/06
CPC分类号： G11C8/10 , G11C8/08 , G11C8/14 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11568
摘要： A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.
摘要翻译：一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线，并且第一字线可以在第一和第二半导体层之间。第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。

6. 发明申请

US20110300683A1 Semiconductor device and method of forming the same 有权
公开(公告)号：US20110300683A1
公开(公告)日：2011-12-08
申请号：US13137420
申请日：2011-08-15
申请人： Jun-Beom Park , Soon-Moon Jung , Ki-Nam Kim
发明人： Jun-Beom Park , Soon-Moon Jung , Ki-Nam Kim
IPC分类号： H01L45/00
CPC分类号： H01L27/24 , Y10S977/774
摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.

7. 发明申请

US20060148153A1 Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses and related devices 有权
标题翻译：制造具有不同压缩应力的绝缘层和相关器件的半导体器件的方法
公开(公告)号：US20060148153A1
公开(公告)日：2006-07-06
申请号：US11322440
申请日：2005-12-30
申请人： Hyung-Shin Kwon , Dong-Won Lee , Jun-Beom Park
发明人： Hyung-Shin Kwon , Dong-Won Lee , Jun-Beom Park
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807
摘要： Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substrate. A first insulating layer is provided on the NMOS transistor. The first insulating layer has a first compressive stress. A second insulating layer is provided on the PMOS transistor. The second insulating layer has a second compressive stress and a stress relief ratio higher than a stress relief ratio of the first insulating layer. A thermal treatment process is performed on the first insulating layer and the second insulating layer such that the second compressive stress of the second insulating layer is lower than the first compressive stress of the first insulating layer. Related devices are also provided.
摘要翻译：提供制造半导体器件的方法。 NMOS晶体管和PMOS晶体管设置在基板上。 NMOS晶体管位于衬底的NMOS区域上，PMOS晶体管位于衬底的PMOS区域上。第一绝缘层设置在NMOS晶体管上。第一绝缘层具有第一压缩应力。第二绝缘层设置在PMOS晶体管上。第二绝缘层具有比第一绝缘层的应力消除比高的第二压缩应力和应力消除比。在第一绝缘层和第二绝缘层上进行热处理工艺，使得第二绝缘层的第二压缩应力低于第一绝缘层的第一压缩应力。还提供了相关设备。

8. 发明授权

US08183634B2 Stack-type semiconductor device 有权
标题翻译：堆叠型半导体器件
公开(公告)号：US08183634B2
公开(公告)日：2012-05-22
申请号：US12536775
申请日：2009-08-06
申请人： Jun-Beom Park , Soon-Moon Jung , Han-Soo Kim , Jae-Hoon Jang , Jae-Hun Jeong , Jong-In Yun , Mi-So Hwang
发明人： Jun-Beom Park , Soon-Moon Jung , Han-Soo Kim , Jae-Hoon Jang , Jae-Hun Jeong , Jong-In Yun , Mi-So Hwang
IPC分类号： H01L27/12
CPC分类号： H01L27/0688 , H01L25/0657 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/12 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stack-type semiconductor device and a method of manufacturing the same are provided. The stack-type semiconductor device includes an insulation layer on a single-crystalline substrate, a contact plug penetrating the insulation layer to contact the single-crystalline substrate, an upper semiconductor pattern including an impurity region and a gate structure positioned between the impurity regions on the upper semiconductor pattern. An upper surface of the contact plug contacts a lower surface of the semiconductor pattern. An operation failure of the stack-type semiconductor device is reduced since the upper semiconductor pattern is electrically connected to the single-crystalline semiconductor substrate.
摘要翻译：提供堆叠型半导体器件及其制造方法。堆叠型半导体器件包括在单晶衬底上的绝缘层，穿透绝缘层以接触单晶衬底的接触插塞，包括位于杂质区之间的杂质区和栅结构的上半导体图案上半导体图案。接触插头的上表面接触半导体图案的下表面。由于上半导体图形与单晶半导体衬底电连接，所以堆叠型半导体器件的操作故障减小。

9. 发明授权

US08026504B2 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US08026504B2
公开(公告)日：2011-09-27
申请号：US12379814
申请日：2009-03-02
申请人： Jun-Beom Park , Soon-Moon Jung , Ki-Nam Kim
发明人： Jun-Beom Park , Soon-Moon Jung , Ki-Nam Kim
IPC分类号： H01L47/00
CPC分类号： H01L27/24 , Y10S977/774
摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.
摘要翻译：提供半导体器件及其形成方法。该方法包括制备半导体衬底。可以在半导体衬底上依次形成绝缘层。可以在绝缘层之间形成有源元件。可以在绝缘层中形成公共节点以电连接到有源元件。公共节点和有源元件可以二维重复地布置在半导体衬底上。

10. 发明授权

US08004885B2 Three-dimensional memory device and driving method thereof 失效
标题翻译：三维记忆装置及其驱动方法
公开(公告)号：US08004885B2
公开(公告)日：2011-08-23
申请号：US12418821
申请日：2009-04-06
申请人： Jong-In Yun , Jae-Hoon Jang , Soon-Moon Jung , Han-Soo Kim , Jun-Beom Park , Jae-Hun Jeong
发明人： Jong-In Yun , Jae-Hoon Jang , Soon-Moon Jung , Han-Soo Kim , Jun-Beom Park , Jae-Hun Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427 , H01L27/11551
摘要： A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A well of an unselected layer is biased with a second well voltage higher than the first well voltage.
摘要翻译：提供具有多个层的三维存储器件的驱动方法。选择其中一个图层。所选择的层的阱被第一阱电压偏置。字线电压被施加到所选层的选定字线。未选择的层的阱以比第一阱电压高的第二阱电压偏置。

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