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1. 发明申请

US20100032762A1 Stack-Type Semiconductor Device 有权
标题翻译：堆叠型半导体器件
公开(公告)号：US20100032762A1
公开(公告)日：2010-02-11
申请号：US12536775
申请日：2009-08-06
申请人： Jun-Beom Park , Soon-Moon Jung , Han-Soo Kim , Jae-Hoon Jang , Jae-Hun Jeong , Jong-In Yun , Mi-So Hwang
发明人： Jun-Beom Park , Soon-Moon Jung , Han-Soo Kim , Jae-Hoon Jang , Jae-Hun Jeong , Jong-In Yun , Mi-So Hwang
IPC分类号： H01L27/12
CPC分类号： H01L27/0688 , H01L25/0657 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/12 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stack-type semiconductor device and a method of manufacturing the same are provided. The stack-type semiconductor device includes an insulation layer on a single-crystalline substrate, a contact plug penetrating the insulation layer to contact the single-crystalline substrate, an upper semiconductor pattern including an impurity region and a gate structure positioned between the impurity regions on the upper semiconductor pattern. An upper surface of the contact plug contacts a lower surface of the semiconductor pattern. An operation failure of the stack-type semiconductor device is reduced since the upper semiconductor pattern is electrically connected to the single-crystalline semiconductor substrate.
摘要翻译：提供堆叠型半导体器件及其制造方法。堆叠型半导体器件包括在单晶衬底上的绝缘层，穿透绝缘层以接触单晶衬底的接触插塞，包括位于杂质区之间的杂质区和栅结构的上半导体图案上半导体图案。接触插头的上表面接触半导体图案的下表面。由于上半导体图形与单晶半导体衬底电连接，所以堆叠型半导体器件的操作故障减少。

2. 发明申请

US20090251962A1 Three-Dimensional Memory Device and Driving Method Thereof 失效
标题翻译：三维存储器件及其驱动方法
公开(公告)号：US20090251962A1
公开(公告)日：2009-10-08
申请号：US12418821
申请日：2009-04-06
申请人： Jong-In Yun , Jae-Hoon Jang , Soon-Moon Jung , Han-Soo Kim , Jun-Beom Park , Jae-Hun Jeong
发明人： Jong-In Yun , Jae-Hoon Jang , Soon-Moon Jung , Han-Soo Kim , Jun-Beom Park , Jae-Hun Jeong
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G11C16/3418 , G11C16/3427 , H01L27/11551
摘要： A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A well of an unselected layer is biased with a second well voltage higher than the first well voltage.
摘要翻译：提供具有多个层的三维存储器件的驱动方法。选择其中一个图层。所选择的层的阱被第一阱电压偏置。字线电压被施加到所选层的选定字线。未选择的层的阱以比第一阱电压高的第二阱电压偏置。

3. 发明授权

US08183634B2 Stack-type semiconductor device 有权
标题翻译：堆叠型半导体器件
公开(公告)号：US08183634B2
公开(公告)日：2012-05-22
申请号：US12536775
申请日：2009-08-06
申请人： Jun-Beom Park , Soon-Moon Jung , Han-Soo Kim , Jae-Hoon Jang , Jae-Hun Jeong , Jong-In Yun , Mi-So Hwang
发明人： Jun-Beom Park , Soon-Moon Jung , Han-Soo Kim , Jae-Hoon Jang , Jae-Hun Jeong , Jong-In Yun , Mi-So Hwang
IPC分类号： H01L27/12
CPC分类号： H01L27/0688 , H01L25/0657 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/12 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stack-type semiconductor device and a method of manufacturing the same are provided. The stack-type semiconductor device includes an insulation layer on a single-crystalline substrate, a contact plug penetrating the insulation layer to contact the single-crystalline substrate, an upper semiconductor pattern including an impurity region and a gate structure positioned between the impurity regions on the upper semiconductor pattern. An upper surface of the contact plug contacts a lower surface of the semiconductor pattern. An operation failure of the stack-type semiconductor device is reduced since the upper semiconductor pattern is electrically connected to the single-crystalline semiconductor substrate.
摘要翻译：提供堆叠型半导体器件及其制造方法。堆叠型半导体器件包括在单晶衬底上的绝缘层，穿透绝缘层以接触单晶衬底的接触插塞，包括位于杂质区之间的杂质区和栅结构的上半导体图案上半导体图案。接触插头的上表面接触半导体图案的下表面。由于上半导体图形与单晶半导体衬底电连接，所以堆叠型半导体器件的操作故障减小。

4. 发明授权

US08004885B2 Three-dimensional memory device and driving method thereof 失效
标题翻译：三维记忆装置及其驱动方法
公开(公告)号：US08004885B2
公开(公告)日：2011-08-23
申请号：US12418821
申请日：2009-04-06
申请人： Jong-In Yun , Jae-Hoon Jang , Soon-Moon Jung , Han-Soo Kim , Jun-Beom Park , Jae-Hun Jeong
发明人： Jong-In Yun , Jae-Hoon Jang , Soon-Moon Jung , Han-Soo Kim , Jun-Beom Park , Jae-Hun Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427 , H01L27/11551
摘要： A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A well of an unselected layer is biased with a second well voltage higher than the first well voltage.
摘要翻译：提供具有多个层的三维存储器件的驱动方法。选择其中一个图层。所选择的层的阱被第一阱电压偏置。字线电压被施加到所选层的选定字线。未选择的层的阱以比第一阱电压高的第二阱电压偏置。

5. 发明授权

US08258517B2 Semiconductor device having driving transistors 有权
标题翻译：具有驱动晶体管的半导体器件
公开(公告)号：US08258517B2
公开(公告)日：2012-09-04
申请号：US12473055
申请日：2009-05-27
申请人： Jong-In Yun , Soon-Moon Jung , Han-Soo Kim , Hoo-Sung Cho , Jun-Beom Park , Jae-Hun Jeong
发明人： Jong-In Yun , Soon-Moon Jung , Han-Soo Kim , Hoo-Sung Cho , Jun-Beom Park , Jae-Hun Jeong
IPC分类号： H01L29/08
CPC分类号： H01L21/76224 , H01L21/8221 , H01L27/0688 , H01L27/11526 , H01L27/11529 , H01L27/11551
摘要： One embodiment exemplarily described herein can be generally characterized as a semiconductor device that includes a lower level device layer located over a semiconductor substrate, an interlayer insulating film located over the lower level device layer and an upper level device layer located over the interlayer insulating film. The lower level device layer may include a plurality of devices formed in the substrate. The upper level device layer may include a plurality of semiconductor patterns and at least one device formed in each of the plurality of semiconductor patterns. The plurality of semiconductor patterns may be electrically isolated from each other. Each of the plurality of semiconductor patterns may include at least one active portion and at least one body contact portion electrically connected to the at least one active portion.
摘要翻译：本文示例性描述的一个实施方案通常可以表征为半导体器件，其包括位于半导体衬底上方的较低级器件层，位于下级器件层上的层间绝缘膜和位于层间绝缘膜上方的上位器件层。下层器件层可以包括形成在衬底中的多个器件。上级器件层可以包括多个半导体图案和形成在多个半导体图案中的每一个中的至少一个器件。多个半导体图案可以彼此电隔离。多个半导体图案中的每一个可以包括至少一个有效部分和至少一个电连接到该至少一个有效部分的主体接触部分。

6. 发明授权

US07960844B2 3-dimensional flash memory device, method of fabrication and method of operation 失效
标题翻译： 3维闪存器件，制造方法和操作方法
公开(公告)号：US07960844B2
公开(公告)日：2011-06-14
申请号：US12499980
申请日：2009-07-09
申请人： Young-Chul Jang , Han-Soo Kim , Jae-Hun Jeong , Soon-Moon Jung
发明人： Young-Chul Jang , Han-Soo Kim , Jae-Hun Jeong , Soon-Moon Jung
IPC分类号： H01L23/48
CPC分类号： H01L27/11578 , H01L27/11524 , H01L27/11551 , H02J2007/0049
摘要： Disclosed are a flash memory device and method of operation. The flash memory device includes a bottom memory cell array and a top memory cell array disposed over the bottom memory cell array. The bottom memory cell array includes a bottom semiconductor layer, a bottom well, and a plurality of bottom memory cell units. The top memory cell array includes a top semiconductor layer, a top well, and a plurality of top memory cell units. A well bias line is disposed over the top memory cell array and includes a bottom well bias line and a top well bias line, The bottom well bias line is electrically connected to the bottom well, and the top well bias line is electrically connected to the top well.
摘要翻译：公开了闪存装置和操作方法。闪速存储器件包括底部存储单元阵列和设置在底部存储单元阵列上的顶部存储器单元阵列。底部存储单元阵列包括底部半导体层，底部阱以及多个底部存储单元单元。顶部存储单元阵列包括顶部半导体层，顶部阱以及多个顶部存储单元。井顶偏置线设置在顶部存储单元阵列上，并且包括底部阱偏置线和顶部阱偏置线。底部阱偏置线电连接到底部阱，并且顶部阱偏置线电连接到顶好

7. 发明授权

US07936002B2 Multiple-layer non-volatile memory devices, memory systems employing such devices, and methods of fabrication thereof 有权
标题翻译：多层非易失性存储器件，采用这种器件的存储器系统及其制造方法
公开(公告)号：US07936002B2
公开(公告)日：2011-05-03
申请号：US12456391
申请日：2009-06-16
申请人： Jonghyuk Kim , Han-Soo Kim , YoungSeop Rah , Min-sung Song , Jang Young Chul , Soon-Moon Jung , Wonseok Cho
发明人： Jonghyuk Kim , Han-Soo Kim , YoungSeop Rah , Min-sung Song , Jang Young Chul , Soon-Moon Jung , Wonseok Cho
IPC分类号： H01L29/76 , H01L31/036 , H01L31/112 , H01L29/94 , H01L31/062
CPC分类号： H01L21/82385 , H01L21/8221 , H01L21/823425 , H01L21/823456 , H01L21/823468 , H01L23/481 , H01L23/485 , H01L27/0688 , H01L27/11526 , H01L27/11551 , H01L2224/9202 , H01L21/76898
摘要： In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.
摘要翻译：在多层存储器件中，采用该器件的存储器系统和形成这种器件的方法在第一存储器件层上的第二存储器件层包括包括第二存储单元区域的第二衬底。第二衬底仅包括第二存储单元区域中的单个阱，第二存储单元区域的单阱包括掺杂有第一类型和第二类型之一杂质的半导体材料。单阱限定了第二衬底的第二存储单元区域中的有源区。多个第二电池串被布置在第二有源区域中的第二衬底上。虽然第二存储单元区域仅包括单个阱，但是在第二层的存储单元的编程或擦除操作期间，需要向第二层的衬底中的单个阱施加高电压，高电压将不妨碍第一层，第二层或其它层的外围晶体管的操作，因为它们彼此隔离。结果，第二层的基底可以被制备成具有更薄的轮廓，并且具有更少的加工步骤，导致具有更高密度，更高可靠性和降低制造成本的装置。

8. 发明申请

US20090315095A1 Multiple-layer non-volatile memory devices, memory systems employing such devices, and methods of fabrication thereof 有权
标题翻译：多层非易失性存储器件，采用这种器件的存储器系统及其制造方法
公开(公告)号：US20090315095A1
公开(公告)日：2009-12-24
申请号：US12456391
申请日：2009-06-16
申请人： Jonghyuk Kim , Han-Soo Kim , YoungSeop Rah , Min-sung Song , Jang Young Chul , Soon-Moon Jung , Wonseok Cho
发明人： Jonghyuk Kim , Han-Soo Kim , YoungSeop Rah , Min-sung Song , Jang Young Chul , Soon-Moon Jung , Wonseok Cho
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/82385 , H01L21/8221 , H01L21/823425 , H01L21/823456 , H01L21/823468 , H01L23/481 , H01L23/485 , H01L27/0688 , H01L27/11526 , H01L27/11551 , H01L2224/9202 , H01L21/76898
摘要： In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.
摘要翻译：在多层存储器件中，采用该器件的存储器系统和形成这种器件的方法在第一存储器件层上的第二存储器件层包括包括第二存储单元区域的第二衬底。第二衬底仅包括第二存储单元区域中的单个阱，第二存储单元区域的单阱包括掺杂有第一类型和第二类型之一杂质的半导体材料。单阱限定了第二衬底的第二存储单元区域中的有源区。多个第二电池串被布置在第二有源区域中的第二衬底上。虽然第二存储单元区域仅包括单个阱，但是在第二层的存储单元的编程或擦除操作期间，需要向第二层的衬底中的单个阱施加高电压，高电压将不妨碍第一层，第二层或其它层的外围晶体管的操作，因为它们彼此隔离。结果，第二层的基底可以被制备成具有更薄的轮廓，并且具有更少的加工步骤，导致具有更高密度，更高可靠性和降低制造成本的装置。

9. 发明授权

US08343812B2 Contact structures in substrate having bonded interface, semiconductor device including the same, methods of fabricating the same 失效
标题翻译：具有接合界面的基板中的接触结构，包括该接合界面的半导体器件，其制造方法
公开(公告)号：US08343812B2
公开(公告)日：2013-01-01
申请号：US13204385
申请日：2011-08-05
申请人： Min-Sung Song , Soon-Moon Jung , Han-Soo Kim , Young-Seop Rah , Won-Seok Cho , Yang-Soo Son , Jong-Hyuk Kim , Young-Chul Jang
发明人： Min-Sung Song , Soon-Moon Jung , Han-Soo Kim , Young-Seop Rah , Won-Seok Cho , Yang-Soo Son , Jong-Hyuk Kim , Young-Chul Jang
IPC分类号： H01L21/82
CPC分类号： H01L27/11519 , G11C5/02 , G11C16/0483 , H01L21/76898 , H01L23/481 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/11578 , H01L2924/0002 , H01L2924/00
摘要： On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.
摘要翻译：接触结构的实施例可以包括在下基板上的下绝缘层，下绝缘层上的上基板，穿过上基板以延伸到下绝缘层中的沟槽，在上基板和下绝缘层，槽中的上绝缘层和穿过槽中的上绝缘层的接触插塞延伸到下绝缘层中。

10. 发明申请

US20110171787A1 MULTIPLE-LAYER NON-VOLATILE MEMORY DEVICES, MEMORY SYSTEMS EMPLOYING SUCH DEVICES, AND METHODS OF FABRICATION THEREOF 有权
标题翻译：多层非易失性存储器件，使用这种器件的存储器系统及其制造方法
公开(公告)号：US20110171787A1
公开(公告)日：2011-07-14
申请号：US13069869
申请日：2011-03-23
申请人： Jonghyuk Kim , Han-Soo Kim , YoungSeop Rah , Min-sung Song , Jang Young Chul , Soon-Moon Jung , Wonseok Cho
发明人： Jonghyuk Kim , Han-Soo Kim , YoungSeop Rah , Min-sung Song , Jang Young Chul , Soon-Moon Jung , Wonseok Cho
IPC分类号： H01L21/8246
CPC分类号： H01L21/82385 , H01L21/8221 , H01L21/823425 , H01L21/823456 , H01L21/823468 , H01L23/481 , H01L23/485 , H01L27/0688 , H01L27/11526 , H01L27/11551 , H01L2224/9202 , H01L21/76898
摘要： In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.
摘要翻译：在多层存储器件中，采用该器件的存储器系统和形成这种器件的方法在第一存储器件层上的第二存储器件层包括包括第二存储单元区域的第二衬底。第二衬底仅包括第二存储单元区域中的单个阱，第二存储单元区域的单阱包括掺杂有第一类型和第二类型之一杂质的半导体材料。单阱限定了第二衬底的第二存储单元区域中的有源区。多个第二电池串被布置在第二有源区域中的第二衬底上。虽然第二存储单元区域仅包括单个阱，但是在第二层的存储单元的编程或擦除操作期间，需要向第二层的衬底中的单个阱施加高电压，高电压将不妨碍第一层，第二层或其它层的外围晶体管的操作，因为它们彼此隔离。结果，第二层的基底可以被制备成具有更薄的轮廓，并且具有更少的加工步骤，导致具有更高密度，更高可靠性和降低制造成本的装置。

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