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1. 发明授权

US08183634B2 Stack-type semiconductor device 有权
标题翻译：堆叠型半导体器件
公开(公告)号：US08183634B2
公开(公告)日：2012-05-22
申请号：US12536775
申请日：2009-08-06
申请人： Jun-Beom Park , Soon-Moon Jung , Han-Soo Kim , Jae-Hoon Jang , Jae-Hun Jeong , Jong-In Yun , Mi-So Hwang
发明人： Jun-Beom Park , Soon-Moon Jung , Han-Soo Kim , Jae-Hoon Jang , Jae-Hun Jeong , Jong-In Yun , Mi-So Hwang
IPC分类号： H01L27/12
CPC分类号： H01L27/0688 , H01L25/0657 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/12 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stack-type semiconductor device and a method of manufacturing the same are provided. The stack-type semiconductor device includes an insulation layer on a single-crystalline substrate, a contact plug penetrating the insulation layer to contact the single-crystalline substrate, an upper semiconductor pattern including an impurity region and a gate structure positioned between the impurity regions on the upper semiconductor pattern. An upper surface of the contact plug contacts a lower surface of the semiconductor pattern. An operation failure of the stack-type semiconductor device is reduced since the upper semiconductor pattern is electrically connected to the single-crystalline semiconductor substrate.
摘要翻译：提供堆叠型半导体器件及其制造方法。堆叠型半导体器件包括在单晶衬底上的绝缘层，穿透绝缘层以接触单晶衬底的接触插塞，包括位于杂质区之间的杂质区和栅结构的上半导体图案上半导体图案。接触插头的上表面接触半导体图案的下表面。由于上半导体图形与单晶半导体衬底电连接，所以堆叠型半导体器件的操作故障减小。

2. 发明授权

US08004885B2 Three-dimensional memory device and driving method thereof 失效
标题翻译：三维记忆装置及其驱动方法
公开(公告)号：US08004885B2
公开(公告)日：2011-08-23
申请号：US12418821
申请日：2009-04-06
申请人： Jong-In Yun , Jae-Hoon Jang , Soon-Moon Jung , Han-Soo Kim , Jun-Beom Park , Jae-Hun Jeong
发明人： Jong-In Yun , Jae-Hoon Jang , Soon-Moon Jung , Han-Soo Kim , Jun-Beom Park , Jae-Hun Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427 , H01L27/11551
摘要： A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A well of an unselected layer is biased with a second well voltage higher than the first well voltage.
摘要翻译：提供具有多个层的三维存储器件的驱动方法。选择其中一个图层。所选择的层的阱被第一阱电压偏置。字线电压被施加到所选层的选定字线。未选择的层的阱以比第一阱电压高的第二阱电压偏置。

3. 发明申请

US20100032762A1 Stack-Type Semiconductor Device 有权
标题翻译：堆叠型半导体器件
公开(公告)号：US20100032762A1
公开(公告)日：2010-02-11
申请号：US12536775
申请日：2009-08-06
申请人： Jun-Beom Park , Soon-Moon Jung , Han-Soo Kim , Jae-Hoon Jang , Jae-Hun Jeong , Jong-In Yun , Mi-So Hwang
发明人： Jun-Beom Park , Soon-Moon Jung , Han-Soo Kim , Jae-Hoon Jang , Jae-Hun Jeong , Jong-In Yun , Mi-So Hwang
IPC分类号： H01L27/12
CPC分类号： H01L27/0688 , H01L25/0657 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/12 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stack-type semiconductor device and a method of manufacturing the same are provided. The stack-type semiconductor device includes an insulation layer on a single-crystalline substrate, a contact plug penetrating the insulation layer to contact the single-crystalline substrate, an upper semiconductor pattern including an impurity region and a gate structure positioned between the impurity regions on the upper semiconductor pattern. An upper surface of the contact plug contacts a lower surface of the semiconductor pattern. An operation failure of the stack-type semiconductor device is reduced since the upper semiconductor pattern is electrically connected to the single-crystalline semiconductor substrate.
摘要翻译：提供堆叠型半导体器件及其制造方法。堆叠型半导体器件包括在单晶衬底上的绝缘层，穿透绝缘层以接触单晶衬底的接触插塞，包括位于杂质区之间的杂质区和栅结构的上半导体图案上半导体图案。接触插头的上表面接触半导体图案的下表面。由于上半导体图形与单晶半导体衬底电连接，所以堆叠型半导体器件的操作故障减少。

4. 发明申请

US20090251962A1 Three-Dimensional Memory Device and Driving Method Thereof 失效
标题翻译：三维存储器件及其驱动方法
公开(公告)号：US20090251962A1
公开(公告)日：2009-10-08
申请号：US12418821
申请日：2009-04-06
申请人： Jong-In Yun , Jae-Hoon Jang , Soon-Moon Jung , Han-Soo Kim , Jun-Beom Park , Jae-Hun Jeong
发明人： Jong-In Yun , Jae-Hoon Jang , Soon-Moon Jung , Han-Soo Kim , Jun-Beom Park , Jae-Hun Jeong
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G11C16/3418 , G11C16/3427 , H01L27/11551
摘要： A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A well of an unselected layer is biased with a second well voltage higher than the first well voltage.
摘要翻译：提供具有多个层的三维存储器件的驱动方法。选择其中一个图层。所选择的层的阱被第一阱电压偏置。字线电压被施加到所选层的选定字线。未选择的层的阱以比第一阱电压高的第二阱电压偏置。

5. 发明授权

US07646664B2 Semiconductor device with three-dimensional array structure 有权
标题翻译：具有三维阵列结构的半导体器件
公开(公告)号：US07646664B2
公开(公告)日：2010-01-12
申请号：US11869140
申请日：2007-10-09
申请人： Hoo-Sung Cho , Soon-Moon Jung , Young-Seop Rah , Jae-Hoon Jang , Jae-Hun Jeong , Jun-Beom Park
发明人： Hoo-Sung Cho , Soon-Moon Jung , Young-Seop Rah , Jae-Hoon Jang , Jae-Hun Jeong , Jun-Beom Park
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/08 , G11C8/14 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11568
摘要： A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.
摘要翻译：一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线，并且第一字线可以在第一和第二半导体层之间。第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。

6. 发明申请

US20080084729A1 SEMICONDUCTOR DEVICE WITH THREE-DIMENSIONAL ARRAY STRUCTURE 有权
标题翻译：具有三维阵列结构的半导体器件
公开(公告)号：US20080084729A1
公开(公告)日：2008-04-10
申请号：US11869140
申请日：2007-10-09
申请人： Hoo-Sung Cho , Soon-Moon Jung , Young-Seop Rah , Jae-Hoon Jang , Jae-Hun Jeong , Jun-Beom Park
发明人： Hoo-Sung Cho , Soon-Moon Jung , Young-Seop Rah , Jae-Hoon Jang , Jae-Hun Jeong , Jun-Beom Park
IPC分类号： G11C5/06
CPC分类号： G11C8/10 , G11C8/08 , G11C8/14 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11568
摘要： A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.
摘要翻译：一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线，并且第一字线可以在第一和第二半导体层之间。第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。

7. 发明申请

US20100240209A1 SEMICONDUCTOR DEVICES INCLUDING HYDROGEN IMPLANTATION LAYERS AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：包括氢植入层的半导体器件及其形成方法
公开(公告)号：US20100240209A1
公开(公告)日：2010-09-23
申请号：US12792912
申请日：2010-06-03
申请人： Jae-Hun Jeong , Ki-Nam Kim , Soon-Moon Jung , Jae-Hoon Jang
发明人： Jae-Hun Jeong , Ki-Nam Kim , Soon-Moon Jung , Jae-Hoon Jang
IPC分类号： H01L21/28
CPC分类号： H01L21/26506 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/167 , H01L29/34 , H01L29/40114 , H01L29/40117 , H01L29/7883 , H01L29/792
摘要： Provided are semiconductor devices and methods of forming the same. The semiconductor devices include a substrate further including a hydrogen implantation layer and a gate structure formed on the hydrogen implantation layer to include a first insulating layer, a charge storage layer, a second insulating layer and a conductive layer.
摘要翻译：提供半导体器件及其形成方法。半导体器件包括还包括氢注入层和在氢注入层上形成的包括第一绝缘层，电荷存储层，第二绝缘层和导电层的栅极结构的衬底。

8. 发明授权

US07795651B2 One transistor DRAM device and method of forming the same 有权
标题翻译：一种晶体管DRAM器件及其形成方法
公开(公告)号：US07795651B2
公开(公告)日：2010-09-14
申请号：US12024459
申请日：2008-02-01
申请人： Jae-Hun Jeong , Ki-Nam Kim , Soon-Moon Jung , Jae-Hoon Jang
发明人： Jae-Hun Jeong , Ki-Nam Kim , Soon-Moon Jung , Jae-Hoon Jang
IPC分类号： H01L31/112
CPC分类号： H01L27/10802 , H01L21/8221 , H01L27/0688 , H01L27/108 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.
摘要翻译：一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。

9. 发明申请

US20090233405A1 METHODS OF FORMING NAND-TYPE NONVOLATILE MEMORY DEVICES 有权
标题翻译：形成NAND型非易失性存储器件的方法
公开(公告)号：US20090233405A1
公开(公告)日：2009-09-17
申请号：US12474896
申请日：2009-05-29
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.
摘要翻译：形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层半导体衬底的整个表面使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

10. 发明授权

US07554140B2 Nand-type non-volatile memory device 失效
标题翻译： Nand型非易失性存储器件
公开(公告)号：US07554140B2
公开(公告)日：2009-06-30
申请号：US11651892
申请日：2007-01-10
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L31/062
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.
摘要翻译：提供了一种NAND型非易失性存储器件及其形成方法。在该方法中，多个单元层层叠在半导体基板上。用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。

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