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1. 发明授权

US09202536B2 Three dimensional memory control circuitry 有权
标题翻译：三维存储器控制电路
公开(公告)号：US09202536B2
公开(公告)日：2015-12-01
申请号：US13995044
申请日：2012-03-26
申请人： Mark Helm , Jung Sheng Hoei , Aaron Yip , Dzung Nguyen
发明人： Mark Helm , Jung Sheng Hoei , Aaron Yip , Dzung Nguyen
IPC分类号： G11C16/04 , G11C7/12 , G11C7/18 , G11C8/14 , H01L27/02 , H01L27/06 , H01L27/105 , H01L27/115 , G11C5/02 , G11C5/12 , G11C13/00 , G11C16/24
CPC分类号： G11C16/26 , G11C5/025 , G11C5/12 , G11C7/12 , G11C7/18 , G11C8/14 , G11C13/0002 , G11C13/0004 , G11C13/0023 , G11C16/24 , H01L27/0207 , H01L27/0688 , H01L27/1052 , H01L27/11526 , H01L27/11529 , H01L27/11556 , H01L27/11573 , H01L27/11582 , Y10T29/49155
摘要： An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
摘要翻译：集成电路包括存储器阵列，字线电路，被划分为至少两个子电路以控制存储器阵列;以及位线电路，被划分为至少两个子电路以控制存储器阵列。字线子电路和位线子电路至少部分地与存储器阵列的相应区域重叠。

2. 发明授权

US08526243B2 Configurable digital and analog input/output interface in a memory device 有权
标题翻译：可配置的数字和模拟输入/输出接口在存储设备中
公开(公告)号：US08526243B2
公开(公告)日：2013-09-03
申请号：US13192948
申请日：2011-07-28
申请人： Frankie F. Roohparvar , Vishal Sarin , Jung-Sheng Hoei
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung-Sheng Hoei
IPC分类号： G11C7/10
CPC分类号： G11C11/5621 , G11C5/066 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C7/16
摘要： Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad. One of the two paths on each pad is selected in response to command signals that indicate the nature of the signal being either transmitted to the device or read from the device. Each digital path includes a latch for latching digital input data. Each analog path includes a sample/hold circuit for storing either analog data being read from or analog data being written to the memory device.
摘要翻译：公开了方法和存储器件，例如具有共享相同输入/输出焊盘的模拟路径和数字路径两者的存储器件。响应于指示信号的性质被传送到设备或从设备读取的命令信号来选择每个焊盘上的两个路径中的一个路径。每个数字路径包括用于锁存数字输入数据的锁存器。每个模拟路径包括采样/保持电路，用于存储被读取的模拟数据或被写入存储器件的模拟数据。

3. 发明授权

US08385121B2 Memory adapted to program a number of bits to a memory cell and read a different number of bits from the memory cell 有权
标题翻译：存储器，其适于将多个位编程到存储器单元并从存储器单元读取不同数量的位
公开(公告)号：US08385121B2
公开(公告)日：2013-02-26
申请号：US12948952
申请日：2010-11-18
申请人： Vishal Sarin , Jung-Sheng Hoei , Jonathan Pabustan , Frankie F. Roohparvar
发明人： Vishal Sarin , Jung-Sheng Hoei , Jonathan Pabustan , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C7/16 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C27/005 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642 , G11C2216/14
摘要： A memory has a memory array with a memory cell. The memory is adapted to program a first number of bits into the memory cell. The memory is adapted to sense a second number of bits, different from the first number of bits, from the memory cell.
摘要翻译：存储器具有存储单元的存储器阵列。存储器适于将第一数量的位编程到存储器单元中。存储器适于从存储器单元感测与第一位数不同的第二数量的位。

4. 发明授权

US08379446B2 Memory controller self-calibration for removing systemic influence 有权
标题翻译：内存控制器自校准，用于消除系统影响
公开(公告)号：US08379446B2
公开(公告)日：2013-02-19
申请号：US13217492
申请日：2011-08-25
申请人： Frankie F. Roohparvar , Vishal Sarin , Jung-Sheng Hoei
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung-Sheng Hoei
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C16/04 , G11C16/20 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.
摘要翻译：通过向所选择的单元写入电压来执行存储器控制器的自校准。对所选单元格周围的相邻单元进行编程。在每个相邻的编程操作之后，读取所选择的单元上的电压，以确定由例如浮动栅极到浮置栅极耦合的系统偏移引起的任何电压变化。这些变化被平均并存储在表中作为用于调整由偏移表示的存储器的特定区域中的编程电压或读取电压的偏移。通过在不同温度下写入单元格并在不同温度读取来确定温度的自校准方法，以生成写入路径和读取路径的温度偏移表。这些偏移表用于在编程期间和读取期间调整与系统温度相关的偏移。

5. 发明授权

US08169832B2 Methods of erase verification for a flash memory device 有权
标题翻译：闪存设备的擦除验证方法
公开(公告)号：US08169832B2
公开(公告)日：2012-05-01
申请号：US12909414
申请日：2010-10-21
申请人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
发明人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
IPC分类号： G11C11/34
CPC分类号： G11C16/344 , G11C16/0483 , G11C16/3445
摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.
摘要翻译：公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。

6. 发明申请

US20120030529A1 REFRESH OF NON-VOLATILE MEMORY CELLS BASED ON FATIGUE CONDITIONS 有权
标题翻译：基于疲劳条件的非易失性记忆细胞再造
公开(公告)号：US20120030529A1
公开(公告)日：2012-02-02
申请号：US13272407
申请日：2011-10-13
申请人： Frankie F. Roohparvar , Vishal Sarin , Jung-Sheng Hoei
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung-Sheng Hoei
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0751 , G06F11/1068 , G11C16/04 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3431 , G11C16/3495 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.
摘要翻译：在一个或多个所公开的实施例中，存储器装置中的存储器单元在疲劳状况的指示时被刷新。在一个这样的实施例中，控制器监视单元的行为参数，并且确定是否有任何参数在每个参数设置的正常范围之外，从而指示疲劳状况。如果任何细胞表示疲劳状况，来自指示疲劳的细胞块的数据被移动到另一个块。在一个实施例中，在写入另一个存储块之前对数据执行错误检测和校正处理。

7. 发明申请

US20110289254A1 CONFIGURABLE DIGITAL AND ANALOG INPUT/OUTPUT INTERFACE IN A MEMORY DEVICE 有权
标题翻译：存储设备中的可配置数字和模拟输入/输出接口
公开(公告)号：US20110289254A1
公开(公告)日：2011-11-24
申请号：US13192948
申请日：2011-07-28
申请人： Frankie F. ROOHPARVAR , Vishal SARIN , Jung-Sheng HOEI
发明人： Frankie F. ROOHPARVAR , Vishal SARIN , Jung-Sheng HOEI
IPC分类号： G06F13/38
CPC分类号： G11C11/5621 , G11C5/066 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C7/16
摘要： Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad. One of the two paths on each pad is selected in response to command signals that indicate the nature of the signal being either transmitted to the device or read from the device. Each digital path includes a latch for latching digital input data. Each analog path includes a sample/hold circuit for storing either analog data being read from or analog data being written to the memory device.
摘要翻译：公开了方法和存储器件，例如具有共享相同输入/输出焊盘的模拟路径和数字路径两者的存储器件。响应于指示信号的性质被传送到设备或从设备读取的命令信号来选择每个焊盘上的两个路径中的一个路径。每个数字路径包括用于锁存数字输入数据的锁存器。每个模拟路径包括采样/保持电路，用于存储被读取的模拟数据或被写入存储器件的模拟数据。

8. 发明申请

US20110242900A1 MEMORY CELL SENSING DEVICES AND METHODS 有权
标题翻译：记忆细胞感测装置和方法
公开(公告)号：US20110242900A1
公开(公告)日：2011-10-06
申请号：US12751575
申请日：2010-03-31
申请人： Jung Sheng Hoei
发明人： Jung Sheng Hoei
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3454 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/32 , G11C27/005 , G11C2211/5621 , G11C2211/5644
摘要： The present disclosure includes methods, devices, and systems for sensing memory cells. One or more embodiments include providing an output of a first counter to a digital-to-analog converter (DAC). An output of the DAC can correspond to a ramping voltage provided to a control gate of the memory cell. An output of a second counter can be provided to sensing circuitry coupled to a sense line of the memory cell. Conduction of the sense line in response to the ramping voltage can be sensed, and an output value of the second counter can be determined in response to the sensed conduction of the sense line.
摘要翻译：本公开包括用于感测存储器单元的方法，装置和系统。一个或多个实施例包括向数模转换器（DAC）提供第一计数器的输出。 DAC的输出可以对应于提供给存储器单元的控制栅极的斜坡电压。可以将第二计数器的输出提供给耦合到存储器单元的感测线的感测电路。可以感测响应于斜坡电压的感测线的传导，并且可以响应于所感测的感测线的传导来确定第二计数器的输出值。

9. 发明授权

US08023334B2 Program window adjust for memory cell signal line delay 有权
标题翻译：程序窗口调整存储单元信号线延迟
公开(公告)号：US08023334B2
公开(公告)日：2011-09-20
申请号：US12262405
申请日：2008-10-31
申请人： Jung-Sheng Hoei , Jonathan Pabustan , Vishal Sarin , William H. Radke , Frankie F. Roohparvar
发明人： Jung-Sheng Hoei , Jonathan Pabustan , Vishal Sarin , William H. Radke , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C5/063 , G11C11/5628 , G11C11/5642 , G11C16/10
摘要： A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Memory cell signal line propagation delay compensation can be accomplished by characterizing the memory cell signal line propagation delay, such as determining an amount of error due to the delay, and pre-compensating the programmed threshold voltage of the memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Alternatively, memory cell signal line propagation delay can be post-compensated for, or the pre-compensation fine tuned, after sensing the threshold voltages of the selected memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Other methods, devices, etc., are also disclosed.
摘要翻译：描述了补偿存储器单元信号线传播延迟的存储器件和编程和/或读取过程，例如增加总体阈值电压范围和可用的非易失性存储器单元状态。可以通过表征存储单元信号线传播延迟来实现存储单元信号线传播延迟补偿，例如确定由于延迟引起的误差量，并且基于误差量预先补偿存储器单元的编程阈值电压由所选存储单元信号线上的存储单元信号线传播延迟和单元位置引起。或者，可以基于由存储器单元信号线传播延迟和单元引起的误差量感测所选择的存储器单元的阈值电压之后，对存储单元信号线传播延迟进行后补偿或预补偿微调所选存储单元信号线上的位置。还公开了其他方法，装置等。

10. 发明授权

US08023332B2 Cell deterioration warning apparatus and method 有权
标题翻译：电池劣化警告装置及方法
公开(公告)号：US08023332B2
公开(公告)日：2011-09-20
申请号：US12706409
申请日：2010-02-16
申请人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
发明人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C16/3404 , G11C11/5621 , G11C16/0483 , G11C27/005
摘要： Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Warning of cell deterioration can be performed using reference cells programmed in accordance with a known pattern such as to approximate deterioration of non-volatile memory cells of the device.
摘要翻译：适于处理和产生表示两个或更多位信息的数据值的模拟数据信号的存储器件和方法有助于相对于器件处理和仅产生指示各个位的二进制数据信号的数据传输速率的增加。这种存储器件的编程包括编程到表示所需位图案的目标阈值电压范围。读取这样的存储器件包括产生指示目标存储器单元的阈值电压的模拟数据信号。可以使用根据已知图案编程的参考单元来执行电池劣化的警告，以便近似装置的非易失性存储单元的劣化。

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