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热词
    • 8. 发明授权
    • M+N bit programming and M+L bit read for M bit memory cells
    • 对M位存储单元进行M + N位编程和M + L位读取
    • US08111550B2
    • 2012-02-07
    • US13005291
    • 2011-01-12
    • Vishal SarinJung-Sheng HoeiFrankie F. Roohparvar
    • Vishal SarinJung-Sheng HoeiFrankie F. Roohparvar
    • G11C16/04
    • G11C16/0483G11C7/16G11C11/5628G11C11/5642G11C16/10G11C16/26G11C16/3418G11C16/3427G11C27/005G11C2211/5641
    • A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory.
    • 描述了存储器件和编程和/或读取过程,其以比所需的更高的阈值电压分辨率编程和/或读取存储器阵列中的单元。 在编程非易失性存储器单元中,这允许在编程期间更准确的阈值电压放置,并且能够对程序干扰进行预补偿,从而提高单元上随后的任何读取或验证操作的准确性。 在读/读存储器单元中,增加的阈值电压分辨率允许更准确地解释存储器单元的编程状态,并且还能够更有效地使用概率数据编码技术,例如卷积码,部分响应最大似然(PRML) 密度奇偶校验(LDPC),Turbo和网格调制编码和/或解码,降低了存储器的总体错误率。