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1. 发明授权

US08719646B2 Non-volatile memory (NVM) reset sequence with built-in read check 有权
标题翻译：非易失性存储器（NVM）复位序列具有内置读取检查功能
公开(公告)号：US08719646B2
公开(公告)日：2014-05-06
申请号：US13459500
申请日：2012-04-30
申请人： Chen He , Kelly K. Taylor
发明人： Chen He , Kelly K. Taylor
IPC分类号： G11C29/00
CPC分类号： G06F11/1417 , G11C16/20 , G11C29/028 , G11C29/08 , G11C2029/0407
摘要： A new, robust non-volatile memory (NVM) reset sequence is provided in accordance with at least one embodiment, which, after reading a Test NVM portion and overwriting NVM configuration registers' default values with the values read from the Test NVM portion, does a read integrity check. If the read integrity check passes, a reset process will conclude. Otherwise, if the read integrity check fails, the reset process will re-try reading the Test NVM and overwriting the NVM configuration registers' default values. If the read integrity check still fails after a maximum number of re-tries, a fail flag will be set, and the predetermined “safe” default values will be reloaded to the NVM configuration registers, thereby assuring that the NVM device is operational.
摘要翻译：根据至少一个实施例提供了一种新的，稳健的非易失性存储器（NVM）复位序列，其中在读取测试NVM部分并且用从NVM部分读取的值覆盖NVM配置寄存器的默认值之后，读完整性检查。如果阅读完整性检查通过，重新设置过程将会结束。否则，如果读完整性检查失败，则复位过程将重新尝试读取测试NVM并覆盖NVM配置寄存器的默认值。如果读取完整性检查在最大重试次数后仍然失败，则将设置失败标志，并将预定的“安全”默认值重新加载到NVM配置寄存器，从而确保NVM设备可操作。

2. 发明申请

US20130290797A1 NON-VOLATILE MEMORY (NVM) RESET SEQUENCE WITH BUILT-IN READ CHECK 有权
标题翻译：非易失性存储器（NVM）复位序列，内置读取检查
公开(公告)号：US20130290797A1
公开(公告)日：2013-10-31
申请号：US13459500
申请日：2012-04-30
申请人： Chen He , Kelly K. Taylor
发明人： Chen He , Kelly K. Taylor
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G06F11/1417 , G11C16/20 , G11C29/028 , G11C29/08 , G11C2029/0407
摘要： A new, robust non-volatile memory (NVM) reset sequence is provided in accordance with at least one embodiment, which, after reading a Test NVM portion and overwriting NVM configuration registers' default values with the values read from the Test NVM portion, does a read integrity check. If the read integrity check passes, a reset process will conclude. Otherwise, if the read integrity check fails, the reset process will re-try reading the Test NVM and overwriting the NVM configuration registers' default values. If the read integrity check still fails after a maximum number of re-tries, a fail flag will be set, and the predetermined “safe” default values will be reloaded to the NVM configuration registers, thereby assuring that the NVM device is operational.
摘要翻译：根据至少一个实施例提供了一种新的，稳健的非易失性存储器（NVM）复位序列，其中在读取测试NVM部分并且用从NVM部分读取的值覆盖NVM配置寄存器的默认值之后，读完整性检查。如果阅读完整性检查通过，重新设置过程将会结束。否则，如果读完整性检查失败，则复位过程将重新尝试读取测试NVM并覆盖NVM配置寄存器的默认值。如果读取完整性检查在最大重试次数后仍然失败，则将设置失败标志，并将预定的“安全”默认值重新加载到NVM配置寄存器，从而确保NVM设备可操作。

3. 发明申请

US20110107010A1 ONE-TIME PROGRAMMABLE MEMORY DEVICE AND METHODS THEREOF 有权
标题翻译：一次可编程存储器件及其方法
公开(公告)号：US20110107010A1
公开(公告)日：2011-05-05
申请号：US12608548
申请日：2009-10-29
申请人： Timothy J. Strauss , Kelly K. Taylor
发明人： Timothy J. Strauss , Kelly K. Taylor
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C16/10 , G11C16/22 , G11C16/26 , G11C16/3459 , G11C2216/26
摘要： A portion of a programmable memory device is configured as a one-time programmable (OTP) memory, where in response to a write access to the memory device, a memory controller determines whether the write access is associated with a memory location designated as an OTP memory location. If so, the memory controller performs a read of the memory location, and allows the write access only if each memory cell of the memory location is in an un-programmed state. Thus, only a single write access to an OTP memory location is permitted, and subsequent write attempts are disallowed. Further, to enhance detection of programmed cells, the read of the OTP memory location is performed with a lower read voltage than a read voltage associated with a write access to a non-OTP memory location, thereby improving detection of programmed memory cells in the OTP memory location.
摘要翻译：可编程存储器件的一部分被配置为一次性可编程（OTP）存储器，其中响应于对存储器件的写入访问，存储器控制器确定写访问是否与被指定为OTP的存储器位置相关联内存位置。如果是这样，则存储器控制器执行存储器位置的读取，并且仅当存储器位置的每个存储器单元处于未编程状态时才允许写访问。因此，只允许对OTP存储器位置的单个写入访问，并且不允许后续写入尝试。此外，为了增强对编程单元的检测，OTP存储器位置的读取以比与非OTP存储器位置的写入访问相关联的读取电压更低的读取电压来执行，从而改进对OTP中的编程存储器单元的检测内存位置。

4. 发明申请

US20090019100A1 POPULATION COUNT APPROXIMATION CIRCUIT AND METHOD THEREOF 有权
标题翻译：人口计数近似电路及其方法
公开(公告)号：US20090019100A1
公开(公告)日：2009-01-15
申请号：US11777664
申请日：2007-07-13
申请人： William C. Moyer , Kelly K. Taylor
发明人： William C. Moyer , Kelly K. Taylor
IPC分类号： G06F7/60 , G06F7/50
CPC分类号： G06F7/607
摘要： A circuit and method provides an estimate of a population count (popcount) of a plurality of input bit values. In one form the input bit values represent respective nodes of an integrated circuit. An approximation circuit uses an approximation input stage which receives a plurality of data inputs and has a plurality of logic circuits. Each logic circuit provides a single bit output. The approximation circuit provides monotonic accuracy. A reduction tree receives the single bit outputs of the plurality of logic circuits and provides an approximate count of how many of the plurality of data inputs are asserted. Size and speed are improved by providing the estimate as opposed to an exact value.
摘要翻译：电路和方法提供对多个输入比特值的总体数（估计）的估计。在一种形式中，输入位值表示集成电路的各个节点。近似电路使用接收多个数据输入并具有多个逻辑电路的近似输入级。每个逻辑电路提供单个位输出。近似电路提供单调精度。还原树接收多个逻辑电路的单个位输出，并且提供多个数据输入中有多少被断言的近似计数。通过提供估计而不是精确值来改善尺寸和速度。

5. 发明申请

US20140254285A1 Temperature-Based Adaptive Erase or Program Parallelism 有权
标题翻译：基于温度的自适应擦除或程序并行性
公开(公告)号：US20140254285A1
公开(公告)日：2014-09-11
申请号：US13787799
申请日：2013-03-06
申请人： Richard K. Eguchi , Jon S. Choy , Chen He , Kelly K. Taylor
发明人： Richard K. Eguchi , Jon S. Choy , Chen He , Kelly K. Taylor
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C7/04 , G11C16/14 , G11C16/30 , G11C16/349
摘要： A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.
摘要翻译：一种方法包括在一个实现中，执行存储器操作以使用电荷泵的电压将存储器阵列的存储器单元置于第一逻辑状态。使用电荷泵的电压对存储器单元执行一部分操作。将存储器阵列的温度与阈值进行比较。如果温度高于参考电平，则通过仅向减少数量的存储单元提供电压来减小电荷泵上的负载。

6. 发明授权

US08261011B2 One-time programmable memory device and methods thereof 有权
标题翻译：一次性可编程存储器件及其方法
公开(公告)号：US08261011B2
公开(公告)日：2012-09-04
申请号：US12608548
申请日：2009-10-29
申请人： Timothy J. Strauss , Kelly K. Taylor
发明人： Timothy J. Strauss , Kelly K. Taylor
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C16/22 , G11C16/26 , G11C16/3459 , G11C2216/26
摘要： A portion of a programmable memory device is configured as a one-time programmable (OTP) memory, where in response to a write access to the memory device, a memory controller determines whether the write access is associated with a memory location designated as an OTP memory location. If so, the memory controller performs a read of the memory location, and allows the write access only if each memory cell of the memory location is in an un-programmed state. Thus, only a single write access to an OTP memory location is permitted, and subsequent write attempts are disallowed. Further, to enhance detection of programmed cells, the read of the OTP memory location is performed with a lower read voltage than a read voltage associated with a write access to a non-OTP memory location, thereby improving detection of programmed memory cells in the OTP memory location.
摘要翻译：可编程存储器件的一部分被配置为一次性可编程（OTP）存储器，其中响应于对存储器件的写入访问，存储器控制器确定写访问是否与被指定为OTP的存储器位置相关联内存位置。如果是这样，则存储器控制器执行存储器位置的读取，并且仅当存储器位置的每个存储器单元处于未编程状态时才允许写访问。因此，只允许对OTP存储器位置的单个写入访问，并且不允许后续写入尝试。此外，为了增强对编程单元的检测，OTP存储器位置的读取以比与非OTP存储器位置的写入访问相关联的读取电压更低的读取电压来执行，从而改进对OTP中的编程存储器单元的检测内存位置。

7. 发明授权

US07958173B2 Population count approximation circuit and method thereof 有权
标题翻译：人口数近似电路及其方法
公开(公告)号：US07958173B2
公开(公告)日：2011-06-07
申请号：US11777664
申请日：2007-07-13
申请人： William C. Moyer , Kelly K. Taylor
发明人： William C. Moyer , Kelly K. Taylor
IPC分类号： G06F7/00
CPC分类号： G06F7/607
摘要： A circuit and method provides an estimate of a population count (popcount) of a plurality of input bit values. In one form the input bit values represent respective nodes of an integrated circuit. An approximation circuit uses an approximation input stage which receives a plurality of data inputs and has a plurality of logic circuits. Each logic circuit provides a single bit output. The approximation circuit provides monotonic accuracy. A reduction tree receives the single bit outputs of the plurality of logic circuits and provides an approximate count of how many of the plurality of data inputs are asserted. Size and speed are improved by providing the estimate as opposed to an exact value.
摘要翻译：电路和方法提供对多个输入比特值的总体数（估计）的估计。在一种形式中，输入位值表示集成电路的各个节点。近似电路使用接收多个数据输入并具有多个逻辑电路的近似输入级。每个逻辑电路提供单个位输出。近似电路提供单调精度。还原树接收多个逻辑电路的单个位输出，并且提供多个数据输入中有多少被断言的近似计数。通过提供估计而不是精确值来改善尺寸和速度。

8. 发明授权

US07931190B2 Circuit and method for correlated inputs to a population count circuit 有权
标题翻译：电路和方法，用于与人口计数电路相关的输入
公开(公告)号：US07931190B2
公开(公告)日：2011-04-26
申请号：US11777650
申请日：2007-07-13
申请人： William C. Moyer , Kelly K. Taylor
发明人： William C. Moyer , Kelly K. Taylor
IPC分类号： G06C29/00
CPC分类号： G06F7/607
摘要： A circuit includes a plurality of selection circuits. Each of the plurality of selection circuits has a first input, a second input, a control input, and an output. Each of the first inputs receives one of a plurality of correlated signals. Each of the second inputs receives one of a plurality of uncorrelated signals. Each of the control inputs receives a correlation mode control signal, and each of the outputs provides the one of the plurality of correlated signals or the one of the plurality of uncorrelated signals based on the correlation mode control signal. The circuit further includes a population count circuit having a plurality of data inputs coupled to receive the outputs of the plurality of selection circuits. The population count circuit provides a population count for the plurality of data inputs. The population count may be an approximate count or an accurate count.
摘要翻译：电路包括多个选择电路。多个选择电路中的每一个具有第一输入，第二输入，控制输入和输出。每个第一输入端接收多个相关信号中的一个。每个第二输入接收多个不相关信号中的一个。每个控制输入接收相关模式控制信号，并且每个输出基于相关模式控制信号提供多个相关信号中的一个或多个不相关信号中的一个。电路还包括具有耦合以接收多个选择电路的输出的多个数据输入的总体计数电路。人口计数电路为多个数据输入提供总体计数。人口数量可能是近似计数或准确计数。

9. 发明授权

US09224478B2 Temperature-based adaptive erase or program parallelism 有权
标题翻译：基于温度的自适应擦除或程序并行
公开(公告)号：US09224478B2
公开(公告)日：2015-12-29
申请号：US13787799
申请日：2013-03-06
申请人： Richard K. Eguchi , Jon S. Choy , Chen He , Kelly K. Taylor
发明人： Richard K. Eguchi , Jon S. Choy , Chen He , Kelly K. Taylor
IPC分类号： G11C16/04 , G11C16/10 , G11C7/04 , G11C16/14 , G11C16/30 , G11C16/34
CPC分类号： G11C16/10 , G11C7/04 , G11C16/14 , G11C16/30 , G11C16/349
摘要： A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.
摘要翻译：一种方法包括在一个实现中，执行存储器操作以使用电荷泵的电压将存储器阵列的存储器单元置于第一逻辑状态。使用电荷泵的电压对存储器单元执行一部分操作。将存储器阵列的温度与阈值进行比较。如果温度高于参考电平，则通过仅向减少数量的存储单元提供电压来减小电荷泵上的负载。

10. 发明申请

US20150067314A1 SECURE FIRMWARE FLASH CONTROLLER 审中-公开
标题翻译：安全固件闪存控制器
公开(公告)号：US20150067314A1
公开(公告)日：2015-03-05
申请号：US14015889
申请日：2013-08-30
申请人： Timothy J. Strauss , Thomas Jew , Kelly K. Taylor
发明人： Timothy J. Strauss , Thomas Jew , Kelly K. Taylor
IPC分类号： G06F21/57
CPC分类号： G06F21/572
摘要： A microcontroller that includes a secure firmware flash controller is provided. The secure firmware flash controller utilizes a hardware assisted boot sequence that performs a firmware code validation. If the firmware code fails validation for any reason, the firmware flash controller locks out access to the firmware RAM and firmware flash controller, and passes control back to the microcontroller for further measures that are protected by security protocols on the microcontroller.
摘要翻译：提供了一个包含安全固件闪存控制器的微控制器。安全固件闪存控制器利用执行固件代码验证的硬件辅助引导顺序。如果固件代码由于任何原因验证失败，固件闪存控制器锁定对固件RAM和固件闪存控制器的访问，并将控制权传回微控制器，以获得受微控制器上安全协议保护的更多措施。

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