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1. 发明授权

US09224478B2 Temperature-based adaptive erase or program parallelism 有权
标题翻译：基于温度的自适应擦除或程序并行
公开(公告)号：US09224478B2
公开(公告)日：2015-12-29
申请号：US13787799
申请日：2013-03-06
申请人： Richard K. Eguchi , Jon S. Choy , Chen He , Kelly K. Taylor
发明人： Richard K. Eguchi , Jon S. Choy , Chen He , Kelly K. Taylor
IPC分类号： G11C16/04 , G11C16/10 , G11C7/04 , G11C16/14 , G11C16/30 , G11C16/34
CPC分类号： G11C16/10 , G11C7/04 , G11C16/14 , G11C16/30 , G11C16/349
摘要： A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.
摘要翻译：一种方法包括在一个实现中，执行存储器操作以使用电荷泵的电压将存储器阵列的存储器单元置于第一逻辑状态。使用电荷泵的电压对存储器单元执行一部分操作。将存储器阵列的温度与阈值进行比较。如果温度高于参考电平，则通过仅向减少数量的存储单元提供电压来减小电荷泵上的负载。

2. 发明申请

US20140254285A1 Temperature-Based Adaptive Erase or Program Parallelism 有权
标题翻译：基于温度的自适应擦除或程序并行性
公开(公告)号：US20140254285A1
公开(公告)日：2014-09-11
申请号：US13787799
申请日：2013-03-06
申请人： Richard K. Eguchi , Jon S. Choy , Chen He , Kelly K. Taylor
发明人： Richard K. Eguchi , Jon S. Choy , Chen He , Kelly K. Taylor
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C7/04 , G11C16/14 , G11C16/30 , G11C16/349
摘要： A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.
摘要翻译：一种方法包括在一个实现中，执行存储器操作以使用电荷泵的电压将存储器阵列的存储器单元置于第一逻辑状态。使用电荷泵的电压对存储器单元执行一部分操作。将存储器阵列的温度与阈值进行比较。如果温度高于参考电平，则通过仅向减少数量的存储单元提供电压来减小电荷泵上的负载。

3. 发明授权

US08289773B2 Non-volatile memory (NVM) erase operation with brownout recovery technique 有权
标题翻译：具有欠压恢复技术的非易失性存储器（NVM）擦除操作
公开(公告)号：US08289773B2
公开(公告)日：2012-10-16
申请号：US12942260
申请日：2010-11-09
申请人： Richard K. Eguchi , Jon S. Choy , Richard K. Glaeser , Chen He , Peter J. Kuhn
发明人： Richard K. Eguchi , Jon S. Choy , Richard K. Glaeser , Chen He , Peter J. Kuhn
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/107 , G11C16/3409 , G11C16/3445 , G11C16/3459
摘要： A method for erasing a non-volatile memory includes: performing a first pre-erase program step on the non-volatile memory; determining that the non-volatile memory failed to program correctly during the first pre-erase program step; performing a first soft program step on the non-volatile memory in response to determining that the non-volatile memory failed to program correctly; determining that the non-volatile memory soft programmed correctly; performing a second pre-erase program step on the non-volatile memory in response to determining that the non-volatile memory soft programmed correctly during the first soft program step; and performing an erase step on the non-volatile memory. The method may be performed using a non-volatile memory controller.
摘要翻译：擦除非易失性存储器的方法包括：在非易失性存储器上执行第一预擦除程序步骤; 在第一预擦除程序步骤期间确定非易失性存储器未能正确编程; 响应于确定非易失性存储器无法正确编程，对非易失性存储器执行第一软程序步骤; 确定非易失性存储器软编程正确; 响应于确定在第一软程序步骤期间正确地编程非易失性存储器的软件，在非易失性存储器上执行第二预擦除程序步骤; 以及对所述非易失性存储器执行擦除步骤。该方法可以使用非易失性存储器控制器来执行。

4. 发明申请

US20140140161A1 NON-VOLATILE MEMORY ROBUST START-UP USING ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：非易失性存储器使用模拟数字转换器进行稳定启动
公开(公告)号：US20140140161A1
公开(公告)日：2014-05-22
申请号：US13679515
申请日：2012-11-16
申请人： Richard K. Eguchi , Jon S. Choy
发明人： Richard K. Eguchi , Jon S. Choy
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C5/14 , G11C16/30 , G11C29/021 , G11C29/028 , G11C2029/0409
摘要： In accordance with at least one embodiment, an onboard analog-to-digital converter (ADC) on a system-on-a-chip (SOC) is utilized to determine whether a charge pump output for a non-volatile memory (NVM) is correct or not. The SOC is directed to wait until the output is within an expected range before moving to the next step in a start-up procedure. If the maximum allowed start-up time is exceeded, an error signal is sent to the SOC such that the application can react to it.
摘要翻译：根据至少一个实施例，利用片上系统（SOC）上的车载模拟 - 数字转换器（ADC）来确定非易失性存储器（NVM）的电荷泵输出是否为正确与否在开始启动过程中移动到下一步之前，SOC被指示等待直到输出在预期范围内。如果超过允许的最大启动时间，则向SOC发送错误信号，以使应用程序能够对其做出反应。

5. 发明授权

US07640389B2 Non-volatile memory having a multiple block erase mode and method therefor 有权
标题翻译：具有多块擦除模式的非易失性存储器及其方法
公开(公告)号：US07640389B2
公开(公告)日：2009-12-29
申请号：US11364129
申请日：2006-02-28
申请人： Richard K. Eguchi , Jon S. Choy
发明人： Richard K. Eguchi , Jon S. Choy
IPC分类号： G06F12/00 , G06F13/28 , G06F13/00
CPC分类号： G06F12/0246
摘要： A non-volatile memory can have multiple blocks erased in parallel for a relatively few number of erase operations. This saves time for the user in the set-up of the memory because the erase operation is relatively slow. Problems with parallel erase relate to different blocks having different program/erase histories with the result that the blocks with different histories erase differently. Thus, after a predetermined number of erase cycles are performed, the ability to parallel erase is prevented. This is achieved by allowing parallel erasing operations until the predetermined number of erase operations have been counted. After that predetermined number has been reached, a parallel erase mode disable signal is generated to prevent further parallel erase cycles. The count and the predetermined number are maintained in a small block of the non-volatile memory that is inaccessible to the user.
摘要翻译：非易失性存储器可以具有并行擦除多个块，用于相对较少数量的擦除操作。这样可以节省用户设置存储器的时间，因为擦除操作相对较慢。并行擦除的问题涉及具有不同程序/擦除历史的不同块，结果是具有不同历史的块被擦除不同。因此，在执行预定数量的擦除周期之后，防止并行擦除的能力。这通过允许并行擦除操作直到预定数量的擦除操作被计数来实现。在达到预定数量之后，产生并行擦除模式禁止信号，以防止进一步的并行擦除周期。计数和预定数量被保持在用户无法访问的非易失性存储器的小块中。

6. 发明授权

US09318161B2 Non-volatile memory robust start-up using analog-to-digital converter 有权
标题翻译：使用模数转换器的非易失性存储器稳健启动
公开(公告)号：US09318161B2
公开(公告)日：2016-04-19
申请号：US13679515
申请日：2012-11-16
申请人： Richard K. Eguchi , Jon S. Choy
发明人： Richard K. Eguchi , Jon S. Choy
IPC分类号： G11C5/14 , G11C16/30 , G11C29/02 , G11C29/04
CPC分类号： G11C5/145 , G11C5/14 , G11C16/30 , G11C29/021 , G11C29/028 , G11C2029/0409
摘要： In accordance with at least one embodiment, an onboard analog-to-digital converter (ADC) on a system-on-a-chip (SOC) is utilized to determine whether a charge pump output for a non-volatile memory (NVM) is correct or not. The SOC is directed to wait until the output is within an expected range before moving to the next step in a start-up procedure. If the maximum allowed start-up time is exceeded, an error signal is sent to the SOC such that the application can react to it.
摘要翻译：根据至少一个实施例，利用片上系统（SOC）上的车载模拟 - 数字转换器（ADC）来确定非易失性存储器（NVM）的电荷泵输出是否为正确与否在开始启动过程中移动到下一步之前，SOC被指示等待直到输出在预期范围内。如果超过允许的最大启动时间，则向SOC发送错误信号，以使应用程序能够对其做出反应。

7. 发明授权

US07649782B2 Non-volatile memory having a dynamically adjustable soft program verify voltage level and method therefor 有权
标题翻译：具有动态可调软件的非易失性存储器验证电压电平及其方法
公开(公告)号：US07649782B2
公开(公告)日：2010-01-19
申请号：US11831168
申请日：2007-07-31
申请人： Richard K. Eguchi , Jon S. Choy
发明人： Richard K. Eguchi , Jon S. Choy
IPC分类号： G11C16/06
CPC分类号： G11C16/344 , G11C16/3409
摘要： An erase operation in a non-volatile memory includes selecting a block on which to perform an erase operation, erasing the selected block, receiving test data corresponding to the selected block, determining a soft program verify voltage level based on the test data, and soft programming the erased selected block using the soft program verify voltage level. A non-volatile memory includes a plurality of blocks, a test block which stores test data corresponding to each of the plurality of blocks, and a flash control coupled to the plurality of blocks and the test block, the flash control determining a soft program verify voltage level for a particular block of the plurality of blocks based on the test data for the particular block when the particular block is being soft programmed.
摘要翻译：非易失性存储器中的擦除操作包括选择执行擦除操作的块，擦除所选择的块，接收与所选块相对应的测试数据，基于测试数据确定软程序验证电压电平，以及软使用软程序验证电压电平对所擦除的选定块进行编程。非易失性存储器包括多个块，存储对应于多个块中的每一个的测试数据的测试块和耦合到多个块和测试块的闪存控制，闪存控制确定软程序验证当特定块被软编程时，基于特定块的测试数据，对于多个块的特定块的电压电平。

8. 发明申请

US20090034339A1 NON-VOLATILE MEMORY HAVING A DYNAMICALLY ADJUSTABLE SOFT PROGRAM VERIFY VOLTAGE LEVEL AND METHOD THEREFOR 有权
标题翻译：具有动态可调软件的非易失性存储器验证电压等级及其方法
公开(公告)号：US20090034339A1
公开(公告)日：2009-02-05
申请号：US11831168
申请日：2007-07-31
申请人： Richard K. Eguchi , Jon S. Choy
发明人： Richard K. Eguchi , Jon S. Choy
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/344 , G11C16/3409
摘要： An erase operation in a non-volatile memory includes selecting a block on which to perform an erase operation, erasing the selected block, receiving test data corresponding to the selected block, determining a soft program verify voltage level based on the test data, and soft programming the erased selected block using the soft program verify voltage level. A non-volatile memory includes a plurality of blocks, a test block which stores test data corresponding to each of the plurality of blocks, and a flash control coupled to the plurality of blocks and the test block, the flash control determining a soft program verify voltage level for a particular block of the plurality of blocks based on the test data for the particular block when the particular block is being soft programmed.
摘要翻译：非易失性存储器中的擦除操作包括选择执行擦除操作的块，擦除所选择的块，接收与所选块相对应的测试数据，基于测试数据确定软程序验证电压电平，以及软使用软程序验证电压电平对所擦除的选定块进行编程。非易失性存储器包括多个块，存储对应于多个块中的每一个的测试数据的测试块和耦合到多个块和测试块的闪存控制，闪存控制确定软程序验证当特定块被软编程时，基于特定块的测试数据，对于多个块的特定块的电压电平。

9. 发明授权

US08516213B2 Method and apparatus for EEPROM emulation for preventing data loss in the event of a flash block failure 有权
标题翻译：用于EEPROM仿真的方法和装置，用于防止闪存块发生故障时的数据丢失
公开(公告)号：US08516213B2
公开(公告)日：2013-08-20
申请号：US12954130
申请日：2010-11-24
申请人： Chen He , Richard K. Eguchi , Daniel Hadad , Katrina M. Prosperi , Jon W. Weilemann, II
发明人： Chen He , Richard K. Eguchi , Daniel Hadad , Katrina M. Prosperi , Jon W. Weilemann, II
IPC分类号： G06F13/00
CPC分类号： G06F11/1666 , G06F12/0246 , G06F2212/7209
摘要： A defect resistant EEPROM emulator (110) uses one or more redundant and/or spare blocks (213) in addition to active and alternate blocks (211, 212) and stores a duplicate copy of EEPROM data records either in the active and redundant blocks or in duplicate rows in the active block to ensure that EEPROM emulation can continue without data loss in the event a catastrophic failure occurs within a block.
摘要翻译：除了有源和交替块（211,212）之外，抗缺陷EEPROM仿真器（110）还使用一个或多个冗余和/或备用块（213），并将EEPROM数据记录的副本存储在主动和冗余块中在活动块中重复一行，以确保在EEPROM中发生灾难性故障的情况下，EEPROM仿真可以继续而没有数据丢失。

10. 发明申请

US20090168541A1 ELECTRICAL ERASABLE PROGRAMMABLE MEMORY TRANSCONDUCTANCE TESTING 有权
标题翻译：电可擦除可编程存储器的交叉测试
公开(公告)号：US20090168541A1
公开(公告)日：2009-07-02
申请号：US11966068
申请日：2007-12-28
申请人： Richard K. Eguchi , Chen He , Ronald J. Syzdek
发明人： Richard K. Eguchi , Chen He , Ronald J. Syzdek
IPC分类号： G11C29/04
CPC分类号： G11C29/50 , G11C16/04 , G11C2029/5002 , G11C2029/5006
摘要： A test method determines if an array of a Flash EEPROM circuit has a bit cell with a transconductance (gm) that is deficient. The method preconditions all bit cells of the array to a particular programmed state and then determines whether any of the bit cells exhibit undesirable operating characteristics by reading each bit cell to determine whether its transconductance is less than desirable.
摘要翻译：测试方法确定闪存EEPROM电路的阵列是否具有缺陷的跨导（gm）的位单元。该方法将阵列的所有比特单元预先调整到特定的编程状态，然后通过读取每个比特单元来确定其中的任何一个比特单元是否表现出不期望的运行特性，以确定其跨导是否小于期望值。

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