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1. 发明申请

US20140254285A1 Temperature-Based Adaptive Erase or Program Parallelism 有权
标题翻译：基于温度的自适应擦除或程序并行性
公开(公告)号：US20140254285A1
公开(公告)日：2014-09-11
申请号：US13787799
申请日：2013-03-06
申请人： Richard K. Eguchi , Jon S. Choy , Chen He , Kelly K. Taylor
发明人： Richard K. Eguchi , Jon S. Choy , Chen He , Kelly K. Taylor
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C7/04 , G11C16/14 , G11C16/30 , G11C16/349
摘要： A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.
摘要翻译：一种方法包括在一个实现中，执行存储器操作以使用电荷泵的电压将存储器阵列的存储器单元置于第一逻辑状态。使用电荷泵的电压对存储器单元执行一部分操作。将存储器阵列的温度与阈值进行比较。如果温度高于参考电平，则通过仅向减少数量的存储单元提供电压来减小电荷泵上的负载。

2. 发明授权

US09224478B2 Temperature-based adaptive erase or program parallelism 有权
标题翻译：基于温度的自适应擦除或程序并行
公开(公告)号：US09224478B2
公开(公告)日：2015-12-29
申请号：US13787799
申请日：2013-03-06
申请人： Richard K. Eguchi , Jon S. Choy , Chen He , Kelly K. Taylor
发明人： Richard K. Eguchi , Jon S. Choy , Chen He , Kelly K. Taylor
IPC分类号： G11C16/04 , G11C16/10 , G11C7/04 , G11C16/14 , G11C16/30 , G11C16/34
CPC分类号： G11C16/10 , G11C7/04 , G11C16/14 , G11C16/30 , G11C16/349
摘要： A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.
摘要翻译：一种方法包括在一个实现中，执行存储器操作以使用电荷泵的电压将存储器阵列的存储器单元置于第一逻辑状态。使用电荷泵的电压对存储器单元执行一部分操作。将存储器阵列的温度与阈值进行比较。如果温度高于参考电平，则通过仅向减少数量的存储单元提供电压来减小电荷泵上的负载。

3. 发明授权

US08289773B2 Non-volatile memory (NVM) erase operation with brownout recovery technique 有权
标题翻译：具有欠压恢复技术的非易失性存储器（NVM）擦除操作
公开(公告)号：US08289773B2
公开(公告)日：2012-10-16
申请号：US12942260
申请日：2010-11-09
申请人： Richard K. Eguchi , Jon S. Choy , Richard K. Glaeser , Chen He , Peter J. Kuhn
发明人： Richard K. Eguchi , Jon S. Choy , Richard K. Glaeser , Chen He , Peter J. Kuhn
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/107 , G11C16/3409 , G11C16/3445 , G11C16/3459
摘要： A method for erasing a non-volatile memory includes: performing a first pre-erase program step on the non-volatile memory; determining that the non-volatile memory failed to program correctly during the first pre-erase program step; performing a first soft program step on the non-volatile memory in response to determining that the non-volatile memory failed to program correctly; determining that the non-volatile memory soft programmed correctly; performing a second pre-erase program step on the non-volatile memory in response to determining that the non-volatile memory soft programmed correctly during the first soft program step; and performing an erase step on the non-volatile memory. The method may be performed using a non-volatile memory controller.
摘要翻译：擦除非易失性存储器的方法包括：在非易失性存储器上执行第一预擦除程序步骤; 在第一预擦除程序步骤期间确定非易失性存储器未能正确编程; 响应于确定非易失性存储器无法正确编程，对非易失性存储器执行第一软程序步骤; 确定非易失性存储器软编程正确; 响应于确定在第一软程序步骤期间正确地编程非易失性存储器的软件，在非易失性存储器上执行第二预擦除程序步骤; 以及对所述非易失性存储器执行擦除步骤。该方法可以使用非易失性存储器控制器来执行。

4. 发明授权

US08842469B2 Method for programming a multi-state non-volatile memory (NVM) 有权
标题翻译：用于编程多状态非易失性存储器（NVM）的方法
公开(公告)号：US08842469B2
公开(公告)日：2014-09-23
申请号：US12942285
申请日：2010-11-09
申请人： Jon S. Choy , Chen He , Michael A. Sadd
发明人： Jon S. Choy , Chen He , Michael A. Sadd
IPC分类号： G11C16/10 , G11C11/56
CPC分类号： G11C16/10 , G11C11/5628
摘要： A method is provided for programming a multi-state flash memory having a plurality of memory cells. A first programming pulse is provided to the flash array; determining a threshold voltage distribution for the plurality of memory cells after providing the first programming pulse. The plurality of memory cells is categorized into at least two bins based on a threshold voltage of each memory cell of the plurality of memory cells. A first voltage is selected for a second programming pulse for programming a first bin of memory cells of the at least two bins, the first voltage based on both a threshold voltage of the first bin and a first target threshold voltage. A second voltage is selected for a third programming pulse for programming a second bin of memory cells of the at least two bins, the second voltage based on both the threshold voltage of the second bin and on a second target threshold voltage.
摘要翻译：提供了一种用于对具有多个存储单元的多状态闪存进行编程的方法。向闪存阵列提供第一编程脉冲; 在提供所述第一编程脉冲之后，确定所述多个存储器单元的阈值电压分布。基于多个存储器单元中的每个存储器单元的阈值电压将多个存储单元分成至少两个箱。为第二编程脉冲选择第一电压，用于对所述至少两个存储体的存储器单元的第一仓进行编程，所述第一电压基于所述第一仓的阈值电压和第一目标阈值电压。为第三编程脉冲选择第二电压，用于根据第二仓的阈值电压和第二目标阈值电压来编程至少两个存储体的第二存储单元的第二存储单元。

5. 发明申请

US20120201082A1 ERASE RAMP PULSE WIDTH CONTROL FOR NON-VOLATILE MEMORY 有权
标题翻译：用于非易失性存储器的擦除脉冲宽度控制
公开(公告)号：US20120201082A1
公开(公告)日：2012-08-09
申请号：US13023713
申请日：2011-02-09
申请人： Jon S. Choy , Chen He
发明人： Jon S. Choy , Chen He
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/16
摘要： A method of erasing a memory block of a non-volatile memory, including setting a pulse width of erase pulses to an initial width, repeatedly applying erase pulses to the memory block until the memory block meets an erase metric or until a maximum number of erase pulses have been applied, gradually adjusting a pulse voltage magnitude of the erase pulses from an initial pulse voltage level to a maximum pulse voltage level, and reducing the width of the erase pulses to less than the initial width when the pulse voltage magnitude reaches an intermediate voltage level between the initial pulse voltage level and the maximum pulse voltage level. Thus, narrow pulses are applied at higher voltage levels to reduce the amount of over erasure of the memory block.
摘要翻译：一种擦除非易失性存储器的存储块的方法，包括将擦除脉冲的脉冲宽度设置为初始宽度，重复地向存储器块施加擦除脉冲，直到存储块满足擦除度量或直到最大擦除次数为止已经施加脉冲，逐渐地将擦除脉冲的脉冲电压幅度从初始脉冲电压电平调整到最大脉冲电压电平，并且当脉冲电压幅度达到中间值时将擦除脉冲的宽度减小到小于初始宽度初始脉冲电压电平与最大脉冲电压电平之间的电压电平。因此，在较高电压电平下施加窄脉冲以减少擦除存储块的量。

6. 发明申请

US20070274116A1 MULTI-LEVEL VOLTAGE ADJUSTMENT 有权
标题翻译：多电平调整
公开(公告)号：US20070274116A1
公开(公告)日：2007-11-29
申请号：US11420095
申请日：2006-05-24
申请人： Jon S. Choy , Chen He
发明人： Jon S. Choy , Chen He
IPC分类号： G11C19/08
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/30 , G11C2211/565
摘要： An adjustable voltage supply (310) may have a plurality of levels of adjustment, such as a coarse select circuit (471) and a fine select circuit (473), to generate an adjustable voltage (e.g. Vout 364 of FIGS. 3 and 4) with fine resolution across a wide voltage range. In one embodiment, the adjustable voltage may be used as an adjustable read voltage to measure the threshold voltages of bitcells in a memory array (300). From the distribution of these threshold voltages, it is possible to determine the marginality of the bitcells with regard to the voltage which is required to read the bitcells. In one embodiment, the adjustable voltage supply (310) may also be used to provide an adjustable voltage to one or more integrated circuit pwells and/or nwells in order to apply electrical stress. An adjustable voltage supply (310) may be used in any desired context, not just memories.
摘要翻译：可调节电压源（310）可以具有多个调整级别，例如粗略选择电路（471）和精细选择电路（473），以产生可调电压（例如图3和图4的Vout 364）在宽电压范围内具有良好的分辨率。在一个实施例中，可调电压可以用作可调节读取电压，以测量存储器阵列（300）中的位单元的阈值电压。根据这些阈值电压的分布，可以确定比特单元关于读取比特单元所需的电压的边缘性。在一个实施例中，可调电压源（310）还可用于向一个或多个集成电路阱和/或n阱提供可调电压，以便施加电应力。可以在任何期望的上下文中使用可调电压源（310），而不仅仅是存储器。

7. 发明授权

US08351276B2 Soft program of a non-volatile memory block 有权
标题翻译：非易失性存储器块的软程序
公开(公告)号：US08351276B2
公开(公告)日：2013-01-08
申请号：US12835309
申请日：2010-07-13
申请人： Jon S. Choy , Chen He , Michael A. Sadd
发明人： Jon S. Choy , Chen He , Michael A. Sadd
IPC分类号： G11C11/34
CPC分类号： G11C16/3468 , G11C16/0483 , G11C16/16
摘要： A method includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage conditions based on the results from soft programming the first subset of bits is selected. A second subset of bits that have been over-erased are soft programmed. The soft programming applies the initial voltage condition to the bits in the second subset of bits. The second subset comprises bits that are still over-erased when the step of selecting occurs. The result is that the soft programming for the second subset may begin at a more optimum point for quickly achieving the needed soft programming to bring all of the bits within the desired erase condition.
摘要翻译：一种方法包括擦除位并识别被擦除过度擦除的位。已经被擦除的位的第一个子集是软编程的。测量第一个子集的软编程的结果。选择基于来自软编程的结果的多个可能的电压条件的初始电压状态。已经被擦除的位的第二个子集是软编程的。软编程将初始电压条件应用于位的第二子集中的位。第二子集包括当选择步骤发生时仍然被擦除的比特。结果是，用于第二子集的软编程可以在更优化的点开始，以便快速实现所需的软编程以使所有位都处于所需的擦除条件。

8. 发明申请

US20120113714A1 METHOD FOR PROGRAMMING A MULTI-STATE NON-VOLATILE MEMORY (NVM) 有权
标题翻译：用于编程多状态非易失性存储器（NVM）的方法
公开(公告)号：US20120113714A1
公开(公告)日：2012-05-10
申请号：US12942285
申请日：2010-11-09
申请人： JON S. CHOY , Chen He , Michael A. Sadd
发明人： JON S. CHOY , Chen He , Michael A. Sadd
IPC分类号： G11C16/12
CPC分类号： G11C16/10 , G11C11/5628
摘要： A method is provided for programming a multi-state flash memory having a plurality of memory cells. A first programming pulse is provided to the flash array; determining a threshold voltage distribution for the plurality of memory cells after providing the first programming pulse. The plurality of memory cells is categorized into at least two bins based on a threshold voltage of each memory cell of the plurality of memory cells. A first voltage is selected for a second programming pulse for programming a first bin of memory cells of the at least two bins, the first voltage based on both a threshold voltage of the first bin and a first target threshold voltage. A second voltage is selected for a third programming pulse for programming a second bin of memory cells of the at least two bins, the second voltage based on both the threshold voltage of the second bin and on a second target threshold voltage.
摘要翻译：提供了一种用于对具有多个存储单元的多状态闪存进行编程的方法。向闪存阵列提供第一编程脉冲; 在提供所述第一编程脉冲之后，确定所述多个存储器单元的阈值电压分布。基于多个存储器单元中的每个存储器单元的阈值电压将多个存储单元分成至少两个箱。为第二编程脉冲选择第一电压，用于对所述至少两个存储体的存储器单元的第一仓进行编程，所述第一电压基于所述第一仓的阈值电压和第一目标阈值电压。为第三编程脉冲选择第二电压，用于根据第二仓的阈值电压和第二目标阈值电压来编程至少两个存储体的第二存储单元的第二存储单元。

9. 发明申请

US20120014179A1 SOFT PROGRAM OF A NON-VOLATILE MEMORY BLOCK 有权
标题翻译：非易失性存储器块的软件程序
公开(公告)号：US20120014179A1
公开(公告)日：2012-01-19
申请号：US12835309
申请日：2010-07-13
申请人： Jon S. Choy , Chen He , Michael A. Sadd
发明人： Jon S. Choy , Chen He , Michael A. Sadd
IPC分类号： G11C16/04
CPC分类号： G11C16/3468 , G11C16/0483 , G11C16/16
摘要： A method includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage conditions based on the results from soft programming the first subset of bits is selected. A second subset of bits that have been over-erased are soft programmed. The soft programming applies the initial voltage condition to the bits in the second subset of bits. The second subset comprises bits that are still over-erased when the step of selecting occurs. The result is that the soft programming for the second subset may begin at a more optimum point for quickly achieving the needed soft programming to bring all of the bits within the desired erase condition.
摘要翻译：一种方法包括擦除位并识别被擦除过度擦除的位。已经被擦除的位的第一个子集是软编程的。测量第一个子集的软编程的结果。选择基于来自软编程的结果的多个可能的电压条件的初始电压状态。已经被擦除的位的第二个子集是软编程的。软编程将初始电压条件应用于位的第二子集中的位。第二子集包括当选择步骤发生时仍然被擦除的比特。结果是，用于第二子集的软编程可以在更优化的点开始，以便快速实现所需的软编程以使所有位都处于所需的擦除条件。

10. 发明授权

US08345485B2 Erase ramp pulse width control for non-volatile memory 有权
标题翻译：擦除非易失性存储器的斜坡脉冲宽度控制
公开(公告)号：US08345485B2
公开(公告)日：2013-01-01
申请号：US13023713
申请日：2011-02-09
申请人： Jon S. Choy , Chen He
发明人： Jon S. Choy , Chen He
IPC分类号： G11C16/04
CPC分类号： G11C16/16
摘要： A method of erasing a memory block of a non-volatile memory, including setting a pulse width of erase pulses to an initial width, repeatedly applying erase pulses to the memory block until the memory block meets an erase metric or until a maximum number of erase pulses have been applied, gradually adjusting a pulse voltage magnitude of the erase pulses from an initial pulse voltage level to a maximum pulse voltage level, and reducing the width of the erase pulses to less than the initial width when the pulse voltage magnitude reaches an intermediate voltage level between the initial pulse voltage level and the maximum pulse voltage level. Thus, narrow pulses are applied at higher voltage levels to reduce the amount of over erasure of the memory block.
摘要翻译：一种擦除非易失性存储器的存储块的方法，包括将擦除脉冲的脉冲宽度设置为初始宽度，重复地向存储器块施加擦除脉冲，直到存储块满足擦除度量或直到最大擦除次数为止已经施加脉冲，逐渐地将擦除脉冲的脉冲电压幅度从初始脉冲电压电平调整到最大脉冲电压电平，并且当脉冲电压幅度达到中间值时将擦除脉冲的宽度减小到小于初始宽度初始脉冲电压电平与最大脉冲电压电平之间的电压电平。因此，在较高电压电平下施加窄脉冲以减少擦除存储块的量。

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