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1. 发明授权

US08271924B1 Self-configuring components on a device 有权
标题翻译：设备上的自配置组件
公开(公告)号：US08271924B1
公开(公告)日：2012-09-18
申请号：US12426895
申请日：2009-04-20
申请人： Kent Orthner , Desmond Ambrose , Geoff Barnes
发明人： Kent Orthner , Desmond Ambrose , Geoff Barnes
IPC分类号： G06F17/50 , G06F15/177 , G06F9/00
CPC分类号： H03K19/017581 , G06F1/24 , G06F9/24 , G06F9/455 , G06F13/10 , G06F15/177 , G06F15/7867 , G06F17/5027 , G06F17/5054 , G06F19/00 , H01L25/00 , H01L2924/0002 , H03K19/0175 , H03K19/1733 , H03K19/177 , H03K19/17748 , H01L2924/00
摘要： Methods and apparatus are provided for allowing components such as buffers, multiplexers, ingress cores, etc. on a device such as a programmable chip to configure themselves based on parameter information. In some examples, self-configuring components obtain parameter information from adjacent components. In other examples, self-configuring components obtain parameter information from a system environment or a processor register. Component self-configuration can occur at a variety of times including preprocessing, simulation, and run-time.
摘要翻译：提供了一种方法和装置，用于允许诸如可编程芯片的装置上的诸如缓冲器，多路复用器，入口核等的组件基于参数信息进行配置。在一些示例中，自配置组件从相邻组件获取参数信息。在其他示例中，自配置组件从系统环境或处理器寄存器获取参数信息。组件自配置可以在各种时间进行，包括预处理，仿真和运行时。

2. 发明授权

US08635570B1 Self-configuring components on a device 有权
标题翻译：设备上的自配置组件
公开(公告)号：US08635570B1
公开(公告)日：2014-01-21
申请号：US13595362
申请日：2012-08-27
申请人： Kent Orthner , Desmond Ambrose , Geoff Barnes
发明人： Kent Orthner , Desmond Ambrose , Geoff Barnes
IPC分类号： G06F17/50 , G06F19/00 , G06F17/24 , G06F13/10 , G06F15/177 , G06F1/24 , H03K19/0175 , H03K19/177 , H01L25/00 , G06F9/455 , G06F9/24
CPC分类号： H03K19/017581 , G06F1/24 , G06F9/24 , G06F9/455 , G06F13/10 , G06F15/177 , G06F15/7867 , G06F17/5027 , G06F17/5054 , G06F19/00 , H01L25/00 , H01L2924/0002 , H03K19/0175 , H03K19/1733 , H03K19/177 , H03K19/17748 , H01L2924/00
摘要： Methods and apparatus are provided for allowing components such as buffers, multiplexers, ingress cores, etc. on a device such as a programmable chip to configure themselves based on parameter information. In some examples, self-configuring components obtain parameter information from adjacent components. In other examples, self-configuring components obtain parameter information from a system environment or a processor register. Component self-configuration can occur at a variety of times including preprocessing, simulation, and run-time.
摘要翻译：提供了一种方法和装置，用于允许诸如可编程芯片的装置上的诸如缓冲器，多路复用器，入口核等的组件基于参数信息进行配置。在一些示例中，自配置组件从相邻组件获取参数信息。在其他示例中，自配置组件从系统环境或处理器寄存器获取参数信息。组件自配置可以在各种时间进行，包括预处理，仿真和运行时。

3. 发明授权

US08069286B1 Flexible on-chip datapath interface having first and second component interfaces wherein communication is determined based on a type of credit condition 有权
标题翻译：具有第一和第二组件接口的灵活的片上数据通路接口，其中根据信用状况的类型来确定通信
公开(公告)号：US08069286B1
公开(公告)日：2011-11-29
申请号：US12902413
申请日：2010-10-12
申请人： Kent Orthner , Desmond Ambrose , Andrew M. Draper
发明人： Kent Orthner , Desmond Ambrose , Andrew M. Draper
IPC分类号： G06F13/00 , G06F15/16 , G06F9/44
CPC分类号： G06F15/7867
摘要： Methods and apparatus are provided for allowing flexible on-chip datapath interfaces on a device. Datapath connections allow data streamlining without any knowledge of channels or packet boundaries. Flexible and modular interface adapters are used to allow component designers to efficiently provide interoperable components without having to adhere to a strict datapath interface specification. Interface adapters from an adapter library are instantiated and configured automatically when two components are connected.
摘要翻译：提供了用于允许在设备上的灵活的片上数据路径接口的方法和装置。数据路径连接允许数据精简，而不需要任何渠道或数据包边界的知识。灵活和模块化的接口适配器用于允许组件设计人员有效提供可互操作的组件，而不必遵守严格的数据通路接口规范。当连接两个组件时，适配器库中的接口适配器将被自动实例化和配置。

4. 发明授权

US08504973B1 Systems and methods for generating a test environment and test system surrounding a design of an integrated circuit 有权
标题翻译：用于生成围绕集成电路设计的测试环境和测试系统的系统和方法
公开(公告)号：US08504973B1
公开(公告)日：2013-08-06
申请号：US13088300
申请日：2011-04-15
申请人： Wai Kheong Leong , Kent Orthner
发明人： Wai Kheong Leong , Kent Orthner
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Systems and methods for generating and using a test environment and a test system surrounding a design are described. The systems and methods may involve using a same application software for creating a design and for receiving a selection to generate the test environment and the test system. In response to receiving the selection, the systems and methods may execute a verification tool to create the test environment and test system. Moreover, a user may not fill in templates of components of the verification tool. The verification tool is integrated within the application software.
摘要翻译：描述了用于生成和使用测试环境的系统和方法以及围绕设计的测试系统。这些系统和方法可以涉及使用相同的应用软件来创建设计和接收生成测试环境和测试系统的选择。响应于接收到选择，系统和方法可以执行验证工具来创建测试环境和测试系统。此外，用户可能不填写验证工具的组件的模板。验证工具集成在应用软件中。

5. 发明授权

US07539967B1 Self-configuring components on a device 有权
标题翻译：设备上的自配置组件
公开(公告)号：US07539967B1
公开(公告)日：2009-05-26
申请号：US11418693
申请日：2006-05-05
申请人： Kent Orthner , Desmond Ambrose , Geoff Barnes
发明人： Kent Orthner , Desmond Ambrose , Geoff Barnes
IPC分类号： G06F17/50 , G06F9/24 , G06F15/177 , G06F1/24 , H03K19/177 , H01L25/00
CPC分类号： H03K19/017581 , G06F1/24 , G06F9/24 , G06F9/455 , G06F13/10 , G06F15/177 , G06F15/7867 , G06F17/5027 , G06F17/5054 , G06F19/00 , H01L25/00 , H01L2924/0002 , H03K19/0175 , H03K19/1733 , H03K19/177 , H03K19/17748 , H01L2924/00
摘要： Methods and apparatus are provided for allowing components such as buffers, multiplexers, ingress cores, etc. on a device such as a programmable chip to configure themselves based on parameter information. In some examples, self-configuring components obtain parameter information from adjacent components. In other examples, self-configuring components obtain parameter information from a system environment or a processor register. Component self-configuration can occur at a variety of times including preprocessing, simulation, and run-time.
摘要翻译：提供了一种方法和装置，用于允许诸如可编程芯片的装置上的诸如缓冲器，多路复用器，入口核等的组件基于参数信息进行配置。在一些示例中，自配置组件从相邻组件获取参数信息。在其他示例中，自配置组件从系统环境或处理器寄存器获取参数信息。组件自配置可以在各种时间进行，包括预处理，仿真和运行时。

6. 发明授权

US09537488B1 Apparatus for configurable interface and associated methods 有权
标题翻译：用于可配置接口和相关方法的设备
公开(公告)号：US09537488B1
公开(公告)日：2017-01-03
申请号：US13105968
申请日：2011-05-12
申请人： Sean R. Atsatt , Kent Orthner , Daniel R. Mansur
发明人： Sean R. Atsatt , Kent Orthner , Daniel R. Mansur
IPC分类号： H03K19/0175 , H03K19/177
CPC分类号： H03K19/017581 , H03K19/17728 , H03K19/17732 , H03K19/17748
摘要： An field programmable gate array (FPGA) includes a circuit implemented using the FPGA fabric. The FPGA further includes another circuit implemented as hardened circuitry. The FPGA also includes a configurable interface circuit that is adapted to couple together the two circuits.
摘要翻译：现场可编程门阵列（FPGA）包括使用FPGA架构实现的电路。 FPGA还包括实现为硬化电路的另一个电路。 FPGA还包括可配置接口电路，其适于将两个电路耦合在一起。

7. 发明授权

US07912085B1 Programmable packet format converter 有权
标题翻译：可编程包格式转换器
公开(公告)号：US07912085B1
公开(公告)日：2011-03-22
申请号：US11906204
申请日：2007-10-01
申请人： Kent Orthner
发明人： Kent Orthner
IPC分类号： H04J3/16 , H04J3/22
CPC分类号： H04L69/22 , H04L69/08 , H04L69/12 , H04L69/18
摘要： A packet format converter (PFC) that can be programmed to perform any one of a multiple number of different packet format conversions is described. According to one embodiment, the PFC includes a pattern state machine and a pattern memory coupled to the pattern state machine. The pattern memory stores pattern memory data including pointer information. The pointer information is either for writing data to be input into the PFC or reading data to be output by the PFC. The pattern state machine is programmed based on the pattern memory data. Also in one embodiment, the PFC further includes a backpressure control for issuing ready and valid signals for the PFC, wherein the ready signal indicates whether the PFC is ready to accept input data and the valid signal indicates whether the PFC has valid data to output.
摘要翻译：描述了可被编程为执行多个不同分组格式转换中的任何一个的分组格式转换器（PFC）。根据一个实施例，PFC包括图案状态机和耦合到图案状态机的图案存储器。模式存储器存储包括指针信息的模式存储器数据。指针信息用于写入要输入到PFC中的数据或读取由PFC输出的数据。模式状态机根据模式存储器数据进行编程。同样在一个实施例中，PFC还包括背压控制，用于发出用于PFC的就绪和有效信号，其中就绪信号指示PFC是否准备好接受输入数据，并且有效信号指示PFC是否具有有效数据以输出。

8. 发明授权

US07827517B1 Automated register definition, builder and integration framework 有权
标题翻译：自动注册定义，构建器和集成框架
公开(公告)号：US07827517B1
公开(公告)日：2010-11-02
申请号：US11419305
申请日：2006-05-19
申请人： Kent Orthner
发明人： Kent Orthner
IPC分类号： G06F17/55 , G06F9/455 , G06F17/50
CPC分类号： G06F17/5045
摘要： A system for designing an integrated circuit is provided. The system includes a plurality of class databases having register information extracted from a register entry tool. A system integration tool is used to integrate the register information from each of the class databases into a system database. The system integration tool essentially consolidates the class databases and maintains a base address for the various components. A system application module includes a number of application tools, which may be referred to as generators. The application tools include, among other tools, a document generator tool, a hardware description language (HDL) generator, a hardware abstraction layer (HAL) generator, and a test framework. A method of designing a circuit is also provided.
摘要翻译：提供了一种用于设计集成电路的系统。该系统包括具有从寄存器输入工具提取的寄存器信息的多个类数据库。系统集成工具用于将每个类数据库的注册信息集成到系统数据库中。系统集成工具基本上整合了类数据库，并为各种组件维护了一个基地址。系统应用模块包括许多应用工具，其可以被称为生成器。应用工具包括文档生成工具，硬件描述语言（HDL）生成器，硬件抽象层（HAL）生成器和测试框架等）。还提供了一种设计电路的方法。

9. 发明授权

US10970248B2 Processing of ethernet packets at a programmable integrated circuit 有权
公开(公告)号：US10970248B2
公开(公告)日：2021-04-06
申请号：US16852958
申请日：2020-04-20
申请人： Kent Orthner , Travis Johnson , Quinn Jacobson , Sarma Jonnavithula
发明人： Kent Orthner , Travis Johnson , Quinn Jacobson , Sarma Jonnavithula
IPC分类号： G06F15/78 , H04W88/08 , H04L12/891 , H04L12/835 , H04L12/925 , H04L12/931
摘要： Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

10. 发明授权

US08659318B1 Systems and methods for implementing tristate signaling by using encapsulated unidirectional signals 有权
标题翻译：通过使用封装的单向信号实现三态信令的系统和方法
公开(公告)号：US08659318B1
公开(公告)日：2014-02-25
申请号：US12889735
申请日：2010-09-24
申请人： Brandon Lewis Gordon , Kent Orthner , Aaron Ferrucci , David Van Brink
发明人： Brandon Lewis Gordon , Kent Orthner , Aaron Ferrucci , David Van Brink
IPC分类号： H03K19/00 , H03K19/0175
CPC分类号： H03M5/18 , H03M5/16
摘要： Systems and methods for implementing tristate signaling are described. The systems include an integrated circuit that further includes a tristate system. The tristate system converts an encapsulated unidirectional signal into a tristate signal. A relation between multiple unidirectional signals and the tristate signal is established by encapsulating the unidirectional signals to represent the tristate signal. The establishment of the relation facilitates control of the tristate signal by controlling the encapsulated unidirectional signals.
摘要翻译：描述了实现三态信令的系统和方法。该系统包括还包括三态系统的集成电路。三态系统将封装的单向信号转换成三态信号。通过封装单向信号来表示三态信号，建立多个单向信号与三态信号之间的关系。该关系的建立便于通过控制封装的单向信号来控制三态信号。

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