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1. 发明授权

US07855563B2 Robust cable connectivity test receiver for high-speed data receiver 有权
标题翻译：用于高速数据接收器的强大的电缆连接测试接收器
公开(公告)号：US07855563B2
公开(公告)日：2010-12-21
申请号：US11766268
申请日：2007-06-21
申请人： Huihao Xu , Louis L. Hsu , Kevin G. Kramer , James D. Rockrohr , Michael A. Sorna
发明人： Huihao Xu , Louis L. Hsu , Kevin G. Kramer , James D. Rockrohr , Michael A. Sorna
IPC分类号： G01R31/00 , H04B3/46
CPC分类号： G01R31/041 , G01R31/026
摘要： A system is provided for detecting a fault in a signal transmission path. In one embodiment, the system can include a variable amplitude signal attenuator which is operable to modify an input signal by variably attenuating a signal voltage swing of the input signal. Desirably, the input signal is attenuated only when transitioning from a high signal voltage level towards a low signal voltage level d variably, such that a larger high-to-low signal voltage swing is attenuated more than a smaller high-to-low signal voltage swing. Desirably, a comparator, which may apply hysteresis to the output signals, may detect a crossing of a reference voltage level by the modified input signal. In this way, when the comparator does not detect an expected crossing of the reference voltage level by the modified input signal, a determination can be made that a fault exists in the signal transmission path.
摘要翻译：提供了一种用于检测信号传输路径中的故障的系统。在一个实施例中，系统可以包括可变幅度信号衰减器，其可操作以通过可变地衰减输入信号的信号电压摆幅来修改输入信号。期望地，只有当从高信号电压电平转换到低信号电压电平d时，输入信号才被衰减，使得较高的高电平到低的信号电压摆幅比较小的高到低信号电压衰减摇摆。期望地，可能对输出信号施加迟滞的比较器可以检测参考电压电平与修改的输入信号的交叉。以这种方式，当比较器没有检测到通过修改的输入信号的参考电压电平的预期交叉时，可以确定在信号传输路径中存在故障。

2. 发明申请

US20080316930A1 Robust Cable Connectivity Test Receiver For High-Speed Data Receiver 有权
标题翻译：用于高速数据接收器的坚固的电缆连接测试接收器
公开(公告)号：US20080316930A1
公开(公告)日：2008-12-25
申请号：US11766268
申请日：2007-06-21
申请人： Huihao Xu , Louis L. Hsu , Kevin G. Kramer , James D. Rockrohr , Michael A. Sorna
发明人： Huihao Xu , Louis L. Hsu , Kevin G. Kramer , James D. Rockrohr , Michael A. Sorna
IPC分类号： G01R31/08
CPC分类号： G01R31/041 , G01R31/026
摘要： A system is provided for detecting a fault in a signal transmission path. In one embodiment, the system can include a variable amplitude signal attenuator which is operable to modify an input signal by variably attenuating a signal voltage swing of the input signal. Desirably, the input signal is attenuated only when transitioning from a high signal voltage level towards a low signal voltage level d variably, such that a larger high-to-low signal voltage swing is attenuated more than a smaller high-to-low signal voltage swing. Desirably, a comparator, which may apply hysteresis to the output signals, may detect a crossing of a reference voltage level by the modified input signal. In this way, when the comparator does not detect an expected crossing of the reference voltage level by the modified input signal, a determination can be made that a fault exists in the signal transmission path.
摘要翻译：提供了一种用于检测信号传输路径中的故障的系统。在一个实施例中，系统可以包括可变幅度信号衰减器，其可操作以通过可变地衰减输入信号的信号电压摆幅来修改输入信号。期望地，只有当从高信号电压电平转换到低信号电压电平d时，输入信号才被衰减，使得较高的高电平到低的信号电压摆幅比较小的高到低的信号电压衰减摇摆。期望地，可能对输出信号施加迟滞的比较器可以检测参考电压电平与修改的输入信号的交叉。以这种方式，当比较器没有检测到通过修改的输入信号的参考电压电平的预期交叉时，可以确定在信号传输路径中存在故障。

3. 发明授权

US5313475A ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme 失效
标题翻译： ECC功能具有独立的高性能部分写入或读/修改/写入和奇偶校验预先接口方案
公开(公告)号：US5313475A
公开(公告)日：1994-05-17
申请号：US785558
申请日：1991-10-31
申请人： Daryl C. Cromer , Gene J. Gaudenzi , Paul C. King , Kevin G. Kramer , Timothy J. Louie
发明人： Daryl C. Cromer , Gene J. Gaudenzi , Paul C. King , Kevin G. Kramer , Timothy J. Louie
IPC分类号： G06F11/10 , G06F12/16 , G06F13/36 , H03M13/00
CPC分类号： G06F11/10 , G06F11/1056
摘要： An error correcting code (ECC) function and a parity interface scheme providing a translation capability between the ECC and parity protocols is implemented for memory systems in personal computers (PCs). The ECC function addresses the problems of interfacing memory with a variety of other components that may communicate in words composed of differing numbers of bytes. A partial write function within an ECC module permits a read/modify/write operation without extra components, at faster speeds and with minimal use of the system bus. An improved parity/ECC protocol interface is implemented by choosing an appropriate ECC code to facilitate parity generation and checking. This is done by selecting a code that contains groupings of data bits corresponding to the desired parity scheme. The ECC XOR trees are modified to allow parity checking and error correction decode simultaneously, thereby eliminating the need for two sets of XOR trees in the interface.
摘要翻译：针对个人计算机（PC）中的存储系统，实施了纠错码（ECC）功能和提供ECC和奇偶校验协议之间的转换能力的奇偶校验接口方案。 ECC功能解决了将存储器与可以以不同字节数组成的单词通信的各种其他组件进行接口的问题。 ECC模块内的部分写入功能允许读取/修改/写入操作，无需额外的组件，速度更快，并且最少使用系统总线。通过选择适当的ECC代码来实现改进的奇偶校验/ ECC协议接口，以便于奇偶校验生成和检查。这通过选择包含对应于所需奇偶校验方案的数据位分组的代码来完成。 ECC XOR树被修改为允许同时进行奇偶校验和纠错解码，从而消除了对接口中两组XOR树的需要。

4. 发明授权

US07603609B2 Method and system for optimized instruction fetch to protect against soft and hard errors 失效
标题翻译：用于优化指令提取的方法和系统，以防止软和硬错误
公开(公告)号：US07603609B2
公开(公告)日：2009-10-13
申请号：US11753127
申请日：2007-05-24
申请人： Jonathan M Haswell , Kevin G Kramer
发明人： Jonathan M Haswell , Kevin G Kramer
IPC分类号： H03M13/00
CPC分类号： G06F11/10
摘要： A method of detecting error during transfer of instructions from a data memory to a computer processor. At the time of the commencement of transmission of the instructions, the raw data signal is checked for an error detection code indicating data corruption. If the error detection code indicates no data corruption, the transmission of the instruction to the computer processor is completed. However, if data corruption is indicated, the raw data signal is substituted with a predetermined reserved signal or instruction and transmitted to the computer processor. An attempt is made to correct the corrupted data in the raw data signal and, if it is corrected, the corrected data signal is subsequently retrieved and the corrected data signal is processed by the computer processor. The corrupted raw data signal in the data memory may be replaced with the corrected data signal.
摘要翻译：一种在从数据存储器传输到计算机处理器的指令传送期间检测错误的方法。在指令的发送开始时，检查原始数据信号是否存在指示数据损坏的错误检测码。如果错误检测码表示没有数据损坏，则完成向计算机处理器发送指令。然而，如果指示数据损坏，原始数据信号被预定的预留信号或指令代替，并被发送到计算机处理器。尝试校正原始数据信号中的损坏的数据，并且如果其被校正，则随后检索校正的数据信号，并且由计算机处理器处理校正的数据信号。数据存储器中损坏的原始数据信号可以用校正的数据信号代替。

5. 发明授权

US07278083B2 Method and system for optimized instruction fetch to protect against soft and hard errors 有权
标题翻译：用于优化指令提取的方法和系统，以防止软和硬错误
公开(公告)号：US07278083B2
公开(公告)日：2007-10-02
申请号：US10604141
申请日：2003-06-27
申请人： Jonathan M. Haswell , Kevin G. Kramer
发明人： Jonathan M. Haswell , Kevin G. Kramer
IPC分类号： H03M13/00
CPC分类号： G06F11/10
摘要： A method of detecting error during transfer of instructions from a data memory to a computer processor. At the time of the commencement of transmission of the instructions, the raw data signal is checked for an error detection code indicating data corruption. If the error detection code indicates no data corruption, the transmission of the instruction to the computer processor is completed. However, if data corruption is indicated, the raw data signal is substituted with a predetermined reserved signal or instruction and transmitted to the computer processor. An attempt is made to correct the corrupted data in the raw data signal and, if it is corrected, the corrected data signal is subsequently retrieved and the corrected data signal is processed by the computer processor. The corrupted raw data signal in the data memory may be replaced with the corrected data signal.
摘要翻译：一种在从数据存储器传输到计算机处理器的指令传送期间检测错误的方法。在指令的发送开始时，检查原始数据信号是否存在指示数据损坏的错误检测码。如果错误检测码表示没有数据损坏，则完成向计算机处理器发送指令。然而，如果指示数据损坏，原始数据信号被预定的预留信号或指令代替，并被发送到计算机处理器。尝试校正原始数据信号中的损坏的数据，并且如果其被校正，则随后检索校正的数据信号，并且由计算机处理器处理校正的数据信号。数据存储器中损坏的原始数据信号可以用校正的数据信号代替。

6. 发明授权

US06987761B2 Inbound data stream controller with pre-recognition of frame sequence 失效
标题翻译：入站数据流控制器，具有帧序列的预识别
公开(公告)号：US06987761B2
公开(公告)日：2006-01-17
申请号：US09683777
申请日：2002-02-13
申请人： Robert M. Bunce , Louis T. Fasano , Christos J. Georgiou , Kevin G. Kramer , Brian J. Schuh
发明人： Robert M. Bunce , Louis T. Fasano , Christos J. Georgiou , Kevin G. Kramer , Brian J. Schuh
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L29/06 , H04L69/22
摘要： A data communication controller processes incoming data frames. The controller includes a pre-processing block for receiving data frames and a frame processing unit coupled to the pre-processing block. The pre-processing block is configured to compare header fields of a current frame with header fields of a previous frame. The pre-processing block provides an output signal to the frame processing unit on the basis of the comparison of the header fields of the current and previous frames. The controller may operate in accordance with the Fiber Channel protocol, and the output signal may include bits to indicate that the current frame is of the same exchange, of the same sequence, and is next in sequence relative to the previous frame.
摘要翻译：数据通信控制器处理传入的数据帧。控制器包括用于接收数据帧的预处理块和耦合到预处理块的帧处理单元。预处理块被配置为将当前帧的报头字段与先前帧的报头字段进行比较。预处理块基于当前帧和前一帧的报头字段的比较，向帧处理单元提供输出信号。控制器可以根据光纤通道协议进行操作，并且输出信号可以包括指示当前帧具有相同序列的相同交换的比特，并且相对于先前帧而言是顺序的。

7. 发明授权

US07873922B2 Structure for robust cable connectivity test receiver for high-speed data receiver 有权
标题翻译：用于高速数据接收机的坚固电缆连接测试接收机的结构
公开(公告)号：US07873922B2
公开(公告)日：2011-01-18
申请号：US11985956
申请日：2007-11-19
申请人： Huihao Xu , Louis L. Hsu , Kevin G. Kramer , James D. Rockrohr , Michael A. Sorna
发明人： Huihao Xu , Louis L. Hsu , Kevin G. Kramer , James D. Rockrohr , Michael A. Sorna
IPC分类号： G06F17/50
CPC分类号： G06F11/24
摘要： A design structure embodied in a machine-readable medium used in a design process may include a system for detecting a fault in a signal transmission path. Such system may include, for example, a hysteresis comparator including a latch having n-type field effect transistor (“NFET”) storage elements. The hysteresis comparator may be operable to detect a crossing of a reference voltage level by an input signal arriving from the signal transmission path such that when the comparator does not detect an expected crossing of the reference voltage level by the input signal, the fault is determined to be detected in the signal transmission path.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构可以包括用于检测信号传输路径中的故障的系统。这种系统可以包括例如包括具有n型场效应晶体管（“NFET”）存储元件的锁存器的滞后比较器。滞后比较器可以用于检测参考电压电平与从信号传输路径到达的输入信号的交叉，使得当比较器没有检测到参考电压电平与输入信号的预期交叉时，确定故障以在信号传输路径中被检测。

8. 发明申请

US20080080603A1 ON-CHIP DETECTION AND MEASUREMENT OF DATA LOCK IN A HIGH SPEED SERIAL DATA LINK 有权
标题翻译：数据锁定在高速串行数据链路中的片上检测和测量
公开(公告)号：US20080080603A1
公开(公告)日：2008-04-03
申请号：US11537053
申请日：2006-09-29
申请人： Robert M. Bunce , William R. Kelly , Kevin G. Kramer , Dinesh B. Nair
发明人： Robert M. Bunce , William R. Kelly , Kevin G. Kramer , Dinesh B. Nair
IPC分类号： H04B17/00
CPC分类号： G06F17/30985
摘要： A method for on-chip detection of data lock and measurement of data lock time in a high-speed serial data link, including: permitting one or more incoming data streams into the high-speed data link; establishing a pattern to be searched in the one or more incoming data streams; comparing patterns in the one or more incoming data streams to a programmable data pattern; holding a repetitive pattern of bits in the one or more incoming data streams by one or more programmable data pattern registers, wherein when one or more occurrences of a byte are detected, an appropriate bit in the one or more programmable data pattern registers is set to indicate the byte's relative position; and filtering false indications in the repetitive pattern by using a byte detection state machine, the state machine controlling and keeping track of a search progress.
摘要翻译：一种用于在高速串行数据链路中片内检测数据锁定和数据锁定时间的测量的方法，包括：允许一个或多个输入数据流进入高速数据链路; 在所述一个或多个输入数据流中建立要搜索的模式; 将一个或多个输入数据流中的模式与可编程数据模式进行比较; 通过一个或多个可编程数据模式寄存器保持所述一个或多个输入数据流中的位的重复模式，其中当检测到一个或多个字节出现时，所述一个或多个可编程数据模式寄存器中的适当位被设置为表示字节的相对位置; 并通过使用字节检测状态机对重复模式中的错误指示进行过滤，状态机控制并跟踪搜索进度。

9. 发明授权

US5107507A Bidirectional buffer with latch and parity capability 失效
标题翻译：双向缓冲器具有锁定和极性能力
公开(公告)号：US5107507A
公开(公告)日：1992-04-21
申请号：US198961
申请日：1988-05-26
申请人： Patrick M. Bland , Mark E. Dean , Gene J. Gaudenzi , Kevin G. Kramer , Susan L. Tempest
发明人： Patrick M. Bland , Mark E. Dean , Gene J. Gaudenzi , Kevin G. Kramer , Susan L. Tempest
IPC分类号： G06F11/10 , G06F13/38 , G06F13/40 , H03K3/288 , H03K19/082
CPC分类号： G06F11/10 , G06F13/4027 , G06F13/4059 , G06F13/4072 , H03K19/0826 , H03K3/288
摘要： A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

10. 发明授权

US07675966B2 On-chip detection and measurement of data lock in a high-speed serial data link 有权
标题翻译：在高速串行数据链路中片内检测和测量数据锁定
公开(公告)号：US07675966B2
公开(公告)日：2010-03-09
申请号：US11537053
申请日：2006-09-29
申请人： Robert M. Bunce , William R. Kelly , Kevin G. Kramer , Dinesh B. Nair
发明人： Robert M. Bunce , William R. Kelly , Kevin G. Kramer , Dinesh B. Nair
IPC分类号： H04B3/46
CPC分类号： G06F17/30985
摘要： A method for on-chip detection of data lock and measurement of data lock time in a high-speed serial data link, including: permitting one or more incoming data streams into the high-speed data link; establishing a pattern to be searched in the one or more incoming data streams; comparing patterns in the one or more incoming data streams to a programmable data pattern; holding a repetitive pattern of bits in the one or more incoming data streams by one or more programmable data pattern registers, wherein when one or more occurrences of a byte are detected, an appropriate bit in the one or more programmable data pattern registers is set to indicate the byte's relative position; and filtering false indications in the repetitive pattern by using a byte detection state machine, the state machine controlling and keeping track of a search progress.
摘要翻译：一种用于在高速串行数据链路中片内检测数据锁定和数据锁定时间的测量的方法，包括：允许一个或多个输入数据流进入高速数据链路; 在所述一个或多个输入数据流中建立要搜索的模式; 将一个或多个输入数据流中的模式与可编程数据模式进行比较; 通过一个或多个可编程数据模式寄存器保持所述一个或多个输入数据流中的位的重复模式，其中当检测到一个或多个字节出现时，所述一个或多个可编程数据模式寄存器中的适当位被设置为表示字节的相对位置; 并通过使用字节检测状态机对重复模式中的错误指示进行过滤，状态机控制并跟踪搜索进度。

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