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1. 发明授权

US5619443A Carry select and input select adder for late arriving data 失效
标题翻译：携带选择和输入选择加法器用于迟到数据
公开(公告)号：US5619443A
公开(公告)日：1997-04-08
申请号：US414062
申请日：1995-03-31
申请人： Eric M. Schwarz , Robert M. Bunce
发明人： Eric M. Schwarz , Robert M. Bunce
IPC分类号： G06F7/50 , G06F7/507
CPC分类号： G06F7/507
摘要： An adder which takes advantage of the early arriving bits of a time skewed operand to provide a result to an add or substract operation without additional latency. Possible partial results are calculated and then selectively combined according to the late arriving data as the late arriving data becomes available. In an embodiment of the present invention, a first operand is partitioned into groups according to the arrival time of the skewed data, and possible partial results for each group are calculated for the full range of partial inputs that affect it. In addition, the high order groups are calculated with and without a borrow (carry) which is propagated from a low order group. Once the delayed partial operands are known and the borrows (carrys) determined the partial results are gated through multiplexers according to the borrows and partial results, and thus the result is provided with a delay similar to the delay in arrival of the skewed operand.
摘要翻译：利用时间偏移操作数的早期到达位提供加法或减法运算的结果的加法器，而没有额外的等待时间。计算可能的部分结果，然后随着晚到数据变得可用，根据迟到的数据选择性地组合。在本发明的一个实施例中，根据偏斜数据的到达时间将第一操作数分成组，并且针对影响其的部分输入的全部范围计算每组的可能部分结果。另外，高阶组是在从低阶组传播的情况下计算出的，而不是借位（进位）。一旦已知延迟的部分操作数，并且根据借位和部分结果通过多路复用器门限确定部分结果，从而为结果提供类似于偏移操作数到达延迟的延迟。

2. 发明授权

US07249206B2 Dynamic memory allocation between inbound and outbound buffers in a protocol handler 失效
标题翻译：在协议处理程序中的入站和出站缓冲区之间的动态内存分配
公开(公告)号：US07249206B2
公开(公告)日：2007-07-24
申请号：US10710414
申请日：2004-07-08
申请人： Mark R. Bilak , Robert M. Bunce , Steven C. Parker , Brian J. Schuh
发明人： Mark R. Bilak , Robert M. Bunce , Steven C. Parker , Brian J. Schuh
IPC分类号： G06F3/00 , G06F12/00
CPC分类号： H04L49/9047 , H04L49/3018 , H04L49/3027 , H04L49/90
摘要： An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems.
摘要翻译：提出了一种用于在网络协议处理器的入站和出站路径之间动态分配存储器以便优化入站和出站缓冲器之间的给定量的存储器的比率的装置和方法。为计算机网络的入站和出站处理器提供专用但可共享的缓冲存储器。管理缓冲存储器，以便动态地改变用于接收和存储输入数据分组或传输输出数据分组的内存部分。使用本发明减少了与常规固定存储器网络系统相关联的数据速率传输和其他存储器访问瓶颈的限制。

3. 发明授权

US07072970B2 Programmable network protocol handler architecture 失效
标题翻译：可编程网络协议处理器架构
公开(公告)号：US07072970B2
公开(公告)日：2006-07-04
申请号：US09682688
申请日：2001-10-05
申请人： Christos J. Georgiou , Monty M. Denneau , Valentina Salapura , Robert M. Bunce
发明人： Christos J. Georgiou , Monty M. Denneau , Valentina Salapura , Robert M. Bunce
IPC分类号： G06F15/16 , H04L12/28 , H04L3/22
CPC分类号： G06F9/5027 , G06F2209/5018 , H04L47/10 , H04L47/125
摘要： An architecture that achieves high speed performance in a network protocol handler combines parallelism and pipelining in multiple programmable processors, along with specialized front-end logic at the network interface that handles time critical protocol operations. The multiple processors are interconnected via high-speed interconnect, and each processor's memory is globally accessible by other processors. Each processor has multiple threads, each capable of fully executing programs. Each processors contains embedded dynamic random access memory (DRAM). Threads within a processor are assigned the processing of various protocol functions in a parallel/pipelined fashion. Data frame processing is done by one or more of the threads to identify relates frames. Related frames are dispatch to the same thread so as to minimize the overhead associated with memory accesses and general protocol processing. The high-speed protocol handler may also provide built-in monitors for examining the activity of its hardware resources and reallocating the workload to the resources that are not heavily used, thus balancing the resource utilization and increasing the workload throughput.
摘要翻译：在网络协议处理器中实现高速性能的架构将多个可编程处理器中的并行性和流水线结合在一起，以及处理时间关键协议操作的网络接口处的专用前端逻辑。多个处理器通过高速互连进行互连，每个处理器的存储器可由其他处理器全局访问。每个处理器有多个线程，每个线程都能完全执行程序。每个处理器都包含嵌入式动态随机存取存储器（DRAM）。处理器中的线程以并行/流水线方式分配各种协议功能的处理。数据帧处理由一个或多个线程完成，以识别关联的帧。相关帧是调度到相同的线程，以便最小化与存储器访问和通用协议处理相关联的开销。高速协议处理器还可以提供用于检查其硬件资源的活动并将工作负载重新分配给未被大量使用的资源的内置监视器，从而平衡资源利用并增加工作负载的吞吐量。

4. 发明授权

US06987761B2 Inbound data stream controller with pre-recognition of frame sequence 失效
标题翻译：入站数据流控制器，具有帧序列的预识别
公开(公告)号：US06987761B2
公开(公告)日：2006-01-17
申请号：US09683777
申请日：2002-02-13
申请人： Robert M. Bunce , Louis T. Fasano , Christos J. Georgiou , Kevin G. Kramer , Brian J. Schuh
发明人： Robert M. Bunce , Louis T. Fasano , Christos J. Georgiou , Kevin G. Kramer , Brian J. Schuh
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L29/06 , H04L69/22
摘要： A data communication controller processes incoming data frames. The controller includes a pre-processing block for receiving data frames and a frame processing unit coupled to the pre-processing block. The pre-processing block is configured to compare header fields of a current frame with header fields of a previous frame. The pre-processing block provides an output signal to the frame processing unit on the basis of the comparison of the header fields of the current and previous frames. The controller may operate in accordance with the Fiber Channel protocol, and the output signal may include bits to indicate that the current frame is of the same exchange, of the same sequence, and is next in sequence relative to the previous frame.
摘要翻译：数据通信控制器处理传入的数据帧。控制器包括用于接收数据帧的预处理块和耦合到预处理块的帧处理单元。预处理块被配置为将当前帧的报头字段与先前帧的报头字段进行比较。预处理块基于当前帧和前一帧的报头字段的比较，向帧处理单元提供输出信号。控制器可以根据光纤通道协议进行操作，并且输出信号可以包括指示当前帧具有相同序列的相同交换的比特，并且相对于先前帧而言是顺序的。

5. 发明授权

US06877048B2 Dynamic memory allocation between inbound and outbound buffers in a protocol handler 失效
标题翻译：在协议处理程序中的入站和出站缓冲区之间的动态内存分配
公开(公告)号：US06877048B2
公开(公告)日：2005-04-05
申请号：US10063018
申请日：2002-03-12
申请人： Mark R. Bilak , Robert M. Bunce , Steven C. Parker , Brian J. Schuh
发明人： Mark R. Bilak , Robert M. Bunce , Steven C. Parker , Brian J. Schuh
IPC分类号： G06F3/00 , H04L12/56
CPC分类号： H04L49/9047 , H04L49/3018 , H04L49/3027 , H04L49/90
摘要： An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems.
摘要翻译：提出了一种用于在网络协议处理器的入站和出站路径之间动态分配存储器以便优化入站和出站缓冲器之间的给定量的存储器的比率的装置和方法。为计算机网络的入站和出站处理器提供专用但可共享的缓冲存储器。管理缓冲存储器，以便动态地改变用于接收和存储输入数据分组或传输输出数据分组的内存部分。使用本发明减少了与常规固定存储器网络系统相关联的数据速率传输和其他存储器访问瓶颈的限制。

6. 发明授权

US06834365B2 Integrated real-time data tracing with low pin count output 有权
标题翻译：具有低引脚数输出的集成实时数据跟踪
公开(公告)号：US06834365B2
公开(公告)日：2004-12-21
申请号：US09907387
申请日：2001-07-17
申请人： Thomas J. Bardsley , Robert M. Bunce , Timothy M. Kemp , Brian J. Schuh
发明人： Thomas J. Bardsley , Robert M. Bunce , Timothy M. Kemp , Brian J. Schuh
IPC分类号： G06F1100
CPC分类号： G06F11/3636 , G06F11/3495
摘要： An integrated circuit real-time data tracing apparatus for analyzing microprocessor based computer systems for monitoring, in real-time, parameters sufficient to define the load and store operations information that the embedded core controller may assert, and process information during events. Integral on this single chip apparatus is a data trace unit designed to access control, address, and data signal lines required to monitor the embedded core controller's activities; perform data tracing independent of instruction tracing; synchronize with an instruction trace stream; allow for selection of multiple ranges for data tracing; report lost events to a FIFO array; and, output strobe signals to give a cycle accurate indication of when an event has been captured.
摘要翻译：一种用于分析基于微处理器的计算机系统的集成电路实时数据跟踪装置，用于实时监测足以定义嵌入式核心控制器可以断言的负载和存储操作信息的参数，以及在事件期间处理信息。该单芯片设备的一体是数据跟踪单元，用于访问监控嵌入式核心控制器活动所需的控制，地址和数据信号线; 执行独立于指令跟踪的数据跟踪; 与指令跟踪流同步; 允许选择多个范围进行数据跟踪; 将丢失的事件报告给FIFO数组; 并且输出选通信号以给出何时捕获事件的循环精确指示。

7. 发明授权

US07675966B2 On-chip detection and measurement of data lock in a high-speed serial data link 有权
标题翻译：在高速串行数据链路中片内检测和测量数据锁定
公开(公告)号：US07675966B2
公开(公告)日：2010-03-09
申请号：US11537053
申请日：2006-09-29
申请人： Robert M. Bunce , William R. Kelly , Kevin G. Kramer , Dinesh B. Nair
发明人： Robert M. Bunce , William R. Kelly , Kevin G. Kramer , Dinesh B. Nair
IPC分类号： H04B3/46
CPC分类号： G06F17/30985
摘要： A method for on-chip detection of data lock and measurement of data lock time in a high-speed serial data link, including: permitting one or more incoming data streams into the high-speed data link; establishing a pattern to be searched in the one or more incoming data streams; comparing patterns in the one or more incoming data streams to a programmable data pattern; holding a repetitive pattern of bits in the one or more incoming data streams by one or more programmable data pattern registers, wherein when one or more occurrences of a byte are detected, an appropriate bit in the one or more programmable data pattern registers is set to indicate the byte's relative position; and filtering false indications in the repetitive pattern by using a byte detection state machine, the state machine controlling and keeping track of a search progress.
摘要翻译：一种用于在高速串行数据链路中片内检测数据锁定和数据锁定时间的测量的方法，包括：允许一个或多个输入数据流进入高速数据链路; 在所述一个或多个输入数据流中建立要搜索的模式; 将一个或多个输入数据流中的模式与可编程数据模式进行比较; 通过一个或多个可编程数据模式寄存器保持所述一个或多个输入数据流中的位的重复模式，其中当检测到一个或多个字节出现时，所述一个或多个可编程数据模式寄存器中的适当位被设置为表示字节的相对位置; 并通过使用字节检测状态机对重复模式中的错误指示进行过滤，状态机控制并跟踪搜索进度。

8. 发明授权

US5627774A Parallel calculation of exponent and sticky bit during normalization 失效
标题翻译：在归一化期间并行计算指数和粘点
公开(公告)号：US5627774A
公开(公告)日：1997-05-06
申请号：US473308
申请日：1995-06-07
申请人： Eric M. Schwarz , Robert M. Bunce , Leon J. Sigal , Hung C. Ngo
发明人： Eric M. Schwarz , Robert M. Bunce , Leon J. Sigal , Hung C. Ngo
IPC分类号： G06F5/01 , G06F7/57 , G06F7/00 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing. The group sticky bits are further multiplexed according to subsequent shift amounts in the fractional dataflow to provide an output sticky bit at substantially the same time as when the final fractional shift amount is available, and thereby at substantially the same time as the normalized fraction.
摘要翻译：根据分数位移数据流，根据将指数分解成部分指数组，实现用于在归一化期间确定分数移位的方法来确定指数的方法，根据分数确定每个部分指数组的所有可能的部分指数值数据流，并且通过根据分数据流选择性地组合来自每个部分指数组的可能部分指数来提供指数。还提供了一种实现在归一化过程中产生粘性位的方法的系统。粘滞位信息根据分数据流进行预先计算和复用。在本发明的一个实施例中，以树形式计算组粘性信号，每组粘性具有与多路复用的移位增量量相对应的多个可能的粘性位。组粘性位根据分数据流中的随后的移位量进一步复用，以在与最终分数移位量可用时基本相同的时间提供输出粘性位，并且因此与归一化分数基本上相同。

9. 发明申请

US20080301336A1 DYNAMIC MEMORY ALLOCATION BETWEEN INBOUND AND OUTBOUND BUFFERS IN A PROTOCOL HANDLER 有权
标题翻译：协议处理器中的内部和外部缓冲区之间的动态内存分配
公开(公告)号：US20080301336A1
公开(公告)日：2008-12-04
申请号：US12183533
申请日：2008-07-31
申请人： Mark R. BILAK , Robert M. Bunce , Steven C. Parker , Brian J. Schuh
发明人： Mark R. BILAK , Robert M. Bunce , Steven C. Parker , Brian J. Schuh
IPC分类号： H04L12/56 , G06F3/00
CPC分类号： H04L49/9047 , H04L49/3018 , H04L49/3027 , H04L49/90
摘要： An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems.
摘要翻译：提出了一种用于在网络协议处理器的入站和出站路径之间动态分配存储器以便优化入站和出站缓冲器之间的给定量的存储器的比率的装置和方法。为计算机网络的入站和出站处理器提供专用但可共享的缓冲存储器。管理缓冲存储器，以便动态地改变用于接收和存储输入数据分组或传输输出数据分组的内存部分。使用本发明减少了与常规固定存储器网络系统相关联的数据速率传输和其他存储器访问瓶颈的限制。

10. 发明申请

US20080080603A1 ON-CHIP DETECTION AND MEASUREMENT OF DATA LOCK IN A HIGH SPEED SERIAL DATA LINK 有权
标题翻译：数据锁定在高速串行数据链路中的片上检测和测量
公开(公告)号：US20080080603A1
公开(公告)日：2008-04-03
申请号：US11537053
申请日：2006-09-29
申请人： Robert M. Bunce , William R. Kelly , Kevin G. Kramer , Dinesh B. Nair
发明人： Robert M. Bunce , William R. Kelly , Kevin G. Kramer , Dinesh B. Nair
IPC分类号： H04B17/00
CPC分类号： G06F17/30985
摘要： A method for on-chip detection of data lock and measurement of data lock time in a high-speed serial data link, including: permitting one or more incoming data streams into the high-speed data link; establishing a pattern to be searched in the one or more incoming data streams; comparing patterns in the one or more incoming data streams to a programmable data pattern; holding a repetitive pattern of bits in the one or more incoming data streams by one or more programmable data pattern registers, wherein when one or more occurrences of a byte are detected, an appropriate bit in the one or more programmable data pattern registers is set to indicate the byte's relative position; and filtering false indications in the repetitive pattern by using a byte detection state machine, the state machine controlling and keeping track of a search progress.
摘要翻译：一种用于在高速串行数据链路中片内检测数据锁定和数据锁定时间的测量的方法，包括：允许一个或多个输入数据流进入高速数据链路; 在所述一个或多个输入数据流中建立要搜索的模式; 将一个或多个输入数据流中的模式与可编程数据模式进行比较; 通过一个或多个可编程数据模式寄存器保持所述一个或多个输入数据流中的位的重复模式，其中当检测到一个或多个字节出现时，所述一个或多个可编程数据模式寄存器中的适当位被设置为表示字节的相对位置; 并通过使用字节检测状态机对重复模式中的错误指示进行过滤，状态机控制并跟踪搜索进度。

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