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1. 发明授权

US07409524B2 System and method for responding to TLB misses 失效
标题翻译：用于响应TLB未命中的系统和方法
公开(公告)号：US07409524B2
公开(公告)日：2008-08-05
申请号：US11205622
申请日：2005-08-17
申请人： Kevin Safford , Rohit Bhatia , Karl Brummel
发明人： Kevin Safford , Rohit Bhatia , Karl Brummel
IPC分类号： G06F12/00
CPC分类号： G06F12/1063 , G06F12/1018
摘要： The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.
摘要翻译：本发明涉及一种改进的微处理器，具有具有多个可以操作以提供虚拟存储器的高速缓存的存储器系统。在微处理器中包括的高速缓冲存储器中的是传统的高速缓冲存储器，其存储由微处理器执行的处理使用的数据和指令，并且通常被布置在高速缓存层级中，以及一个或多个转换后备缓冲器（TLB）高速缓存它存储有限数量的虚拟页面翻译。改进的微处理器还具有额外的高速缓存，用于存储当TLB未命中时被访问的虚拟散列页表（VHPT）。这种VHPT高速缓存的引入消除或至少减少了在发生TLB缺失时微处理器在高速缓存层级或高速缓存之外的其他存储器（例如，主存储器）中寻找信息的需要，从而增强了微处理器速度。

2. 发明申请

US20050240810A1 Off-chip lockstep checking 有权
标题翻译：片外锁定检查
公开(公告)号：US20050240810A1
公开(公告)日：2005-10-27
申请号：US10818994
申请日：2004-04-06
申请人： Kevin Safford , Donald Soltis , Eric Delano
发明人： Kevin Safford , Donald Soltis , Eric Delano
IPC分类号： G06F11/00 , G06F11/16 , G06K19/067
CPC分类号： G06F11/1641 , G06F11/1625 , G06F2201/845
摘要： A system is provided which includes a microprocessor comprising a first processing unit to generate a first output signal and a second processing unit to generate a second output signal, and comparison means, coupled to the microprocessor, to detect whether the first output signal differs from the second output signal.
摘要翻译：提供了一种系统，其包括微处理器，该微处理器包括产生第一输出信号的第一处理单元和用于产生第二输出信号的第二处理单元，以及耦合到微处理器的比较装置，以检测第一输出信号是否与第二输出信号。

3. 发明申请

US20050108509A1 Error detection method and system for processors that employs lockstepped concurrent threads 审中-公开
标题翻译：使用锁定并发线程的处理器的错误检测方法和系统
公开(公告)号：US20050108509A1
公开(公告)日：2005-05-19
申请号：US10714093
申请日：2003-11-13
申请人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
发明人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
IPC分类号： G06F9/318 , G06F9/38 , G06F11/16 , G06F15/00
CPC分类号： G06F9/3885 , G06F9/30181 , G06F9/3863
摘要： A processor that includes an in-order execution architecture for executing at least two instructions per cycle (e.g., 2n instructions are processed per cycle, where n is an integer greater than or equal to one) and at least two symmetric execution units. The processor includes an instruction fetch unit for fetching n instructions (where n is an integer greater than or equal to one) and an instruction decoder for decoding the n instruction. The error detection mechanism includes duplication hardware for duplicating the n instructions into a first bundle of n instructions and a second bundle of n instructions. A first execution unit for executing the first bundle of instructions in a first execution cycle, and a second symmetric execution unit for executing the second bundle of instructions in the first execution cycle are provided. The error detection mechanism also includes comparison hardware for comparing the results of the first execution unit and the results of the second execution unit. The comparison hardware can have an exception unit for generating an exception (e.g., raising a fault) when the results are not the same. A commit unit is provided for committing one of the results when the results are the same.
摘要翻译：一种处理器，其包括用于每个周期执行至少两个指令的按顺序执行架构（例如，每个周期处理2n个指令，其中n是大于或等于1的整数）和至少两个对称执行单元。处理器包括用于取出n个指令（其中n是大于或等于1的整数）的指令获取单元和用于对n指令进行解码的指令解码器。错误检测机制包括用于将n个指令复制到n个指令的第一束和第n个n个指令束中的复制硬件。提供了用于在第一执行周期中执行第一指令集的第一执行单元和用于在第一执行周期中执行第二指令集的第二对称执行单元。错误检测机构还包括用于比较第一执行单元的结果和第二执行单元的结果的比较硬件。当结果不相同时，比较硬件可以具有用于产生异常（例如，引起故障）的异常单元。当结果相同时，提交提交单元用于提交结果之一。

4. 发明授权

US08479029B2 Methods and apparatuses for reducing step loads of processors 失效
公开(公告)号：US08479029B2
公开(公告)日：2013-07-02
申请号：US13167970
申请日：2011-06-24
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

5. 发明申请

US20110252255A1 Methods And Apparatuses For Reducing Step Loads Of Processors 失效
标题翻译：减少处理器阶跃负载的方法和装置
公开(公告)号：US20110252255A1
公开(公告)日：2011-10-13
申请号：US13167970
申请日：2011-06-24
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
摘要翻译：公开了减少处理器的步进负载的方法和装置。方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并将执行限制到指令的子集号码来控制执行期间的电量。一些实施例还可以创建人为活动以为处理器提供最小功率层。装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑的执行期间要处理的指令。

6. 发明授权

US07992017B2 Methods and apparatuses for reducing step loads of processors 有权
标题翻译：减少处理器阶跃负载的方法和装置
公开(公告)号：US07992017B2
公开(公告)日：2011-08-02
申请号：US11900316
申请日：2007-09-11
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/32 , G06F11/30
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
摘要翻译：公开了减少处理器的步进负载的方法和装置。方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并且将执行限制到指令的子集号码来控制执行期间的电量。一些实施例还可以创建人为活动以为处理器提供最小功率层。装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑的执行期间要处理的指令。

7. 发明申请

US20050120278A1 Systems and methods for verifying lockstep operation 审中-公开
标题翻译：验证锁步操作的系统和方法
公开(公告)号：US20050120278A1
公开(公告)日：2005-06-02
申请号：US10717253
申请日：2003-11-19
申请人： Zachary Smith , Kevin Safford , Jeremy Petsinger
发明人： Zachary Smith , Kevin Safford , Jeremy Petsinger
IPC分类号： G06F11/00 , G06F11/26
CPC分类号： G06F11/261
摘要： In one embodiment, a system and a method for verifying lockstep operation pertain to monitoring interface signals, detecting output of a modeled lockstep block, comparing the detected output with an expected output for the lockstep block relative to a current modeled machine state, and flagging a lockstep block error if the detected output does not match the expected output.
摘要翻译：在一个实施例中，用于验证锁步操作的系统和方法涉及监视接口信号，检测建模的锁步块的输出，将检测到的输出与锁步块相对于当前建模的机器状态的预期输出进行比较，并标记如果检测到的输出与预期输出不匹配，则会产生锁步块错误。

8. 发明申请

US20050114735A1 Systems and methods for verifying core determinacy 审中-公开
标题翻译：验证核心确定性的系统和方法
公开(公告)号：US20050114735A1
公开(公告)日：2005-05-26
申请号：US10718123
申请日：2003-11-20
申请人： Zachary Smith , Kevin Safford , Jeremy Petsinger
发明人： Zachary Smith , Kevin Safford , Jeremy Petsinger
IPC分类号： G02B5/10 , G06F11/00 , G06F17/50
CPC分类号： G06F17/5022
摘要： In one embodiment, a core determinacy verification system and a method pertain to extracting data stored in core model structures, comparing the extracted data of one modeled processor core with extracted data of another modeled processor core, determining if any mismatching data will cause core divergence, and facilitating notice of an error if any mismatching data will cause core divergence.
摘要翻译：在一个实施例中，核心确定性验证系统和方法涉及提取存储在核心模型结构中的数据，将提取的一个建模的处理器核心的数据与另一建模的处理器核心的提取数据进行比较，确定是否有任何不匹配的数据将导致核心发散，并且如果任何不匹配的数据将导致核心分歧，便于通知错误。

9. 发明申请

US20070043929A1 System and method for responding to TLB misses 失效
标题翻译：用于响应TLB未命中的系统和方法
公开(公告)号：US20070043929A1
公开(公告)日：2007-02-22
申请号：US11205622
申请日：2005-08-17
申请人： Kevin Safford , Rohit Bhatia , Karl Brummel
发明人： Kevin Safford , Rohit Bhatia , Karl Brummel
IPC分类号： G06F12/00
CPC分类号： G06F12/1063 , G06F12/1018
摘要： The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.
摘要翻译：本发明涉及一种改进的微处理器，具有具有多个可以操作以提供虚拟存储器的高速缓存的存储器系统。在微处理器中包括的高速缓冲存储器中的是传统的高速缓冲存储器，其存储由微处理器执行的处理使用的数据和指令，并且通常被布置在高速缓存层级中，以及一个或多个转换后备缓冲器（TLB）高速缓存它存储有限数量的虚拟页面翻译。改进的微处理器还具有额外的高速缓存，用于存储当TLB未命中时被访问的虚拟散列页表（VHPT）。引入这种VHPT高速缓存消除或者至少减少了当TLB未命中时微处理器在高速缓存层级的高速缓存或微处理器外部的其他存储器（例如，主存储器）中查找信息的需要，从而增强了微处理器速度。

10. 发明申请

US20060036424A1 Method and apparatus for verifying resources shared by multiple processors 审中-公开
标题翻译：用于验证由多个处理器共享的资源的方法和装置
公开(公告)号：US20060036424A1
公开(公告)日：2006-02-16
申请号：US10917764
申请日：2004-08-13
申请人： Jeremy Petsinger , Danny Kwong , Kevin Safford
发明人： Jeremy Petsinger , Danny Kwong , Kevin Safford
IPC分类号： G06F13/10
CPC分类号： G06F9/52 , G06F12/084
摘要： Computer system models and methods for modeling computers that share resources are disclosed herein. One embodiment of the method for modeling a computer system comprises modeling a first shared resource and associating a first model of the first shared resource with a first processor model. A second model of the first shared resource is associated with a second processor model, wherein the first model of the first shared resource is substantially identical to the second model of the first shared resource. Data associated with the first model of the first shared resource is maintained to be equal to the data associated with the second model of the first shared resource.
摘要翻译：本文公开了用于建模共享资源的计算机的计算机系统模型和方法。用于建模计算机系统的方法的一个实施例包括对第一共享资源进行建模并将第一共享资源的第一模型与第一处理器模型相关联。第一共享资源的第二模型与第二处理器模型相关联，其中第一共享资源的第一模型基本上与第一共享资源的第二模型相同。与第一共享资源的第一模型相关联的数据被保持为等于与第一共享资源的第二模型相关联的数据。

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