专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07291857B2 Non-volatile memory 失效
标题翻译：非易失性存储器
公开(公告)号：US07291857B2
公开(公告)日：2007-11-06
申请号：US10967222
申请日：2004-10-19
申请人： Hideyuki Tanaka , Takashi Ohtsuka , Kiyoyuki Morita , Kiyoshi Morimoto
发明人： Hideyuki Tanaka , Takashi Ohtsuka , Kiyoyuki Morita , Kiyoshi Morimoto
IPC分类号： H01L47/00
CPC分类号： H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/16 , H01L45/1625
摘要： A non-volatile memory (1) which comprises an insulating substrate (11) having a plurality of first electrodes (15) extending therethrough from a front surface of the substrate to a rear surface thereof, a second electrode (12) formed on one surface side of the substrate (11), and a recording layer (14) held between the first electrodes (15) and the second electrode (12) and variable in resistance value by electric pulses applied across the first electrodes (15) and the second electrode (12), the plurality of first electrodes (15) being electrically connected to the recording layer (14) in a region constituting a single memory cell (MC). The non-volatile memory (1) can be reduced in power consumption and has great freedom of design and high reliability.
摘要翻译：一种非易失性存储器（1），其包括绝缘基板（11），所述绝缘基板具有从所述基板的前表面延伸穿过其延伸到其后表面的多个第一电极（15），形成在一个表面上的第二电极基板（11）的一侧，以及保持在第一电极（15）和第二电极（12）之间的记录层（14），并且通过施加在第一电极（15）和第二电极（12），所述多个第一电极（15）在构成单个存储单元（MC）的区域中与记录层（14）电连接。非易失性存储器（1）可以降低功耗，并具有很大的设计自由度和高可靠性。

2. 发明授权

US07053693B2 Voltage generating circuit, voltage generating device and semiconductor device using the same, and driving method thereof 有权
标题翻译：电压产生电路，电压产生装置和使用该电压产生装置的半导体装置及其驱动方法
公开(公告)号：US07053693B2
公开(公告)日：2006-05-30
申请号：US10765175
申请日：2004-01-28
申请人： Kenji Toyoda , Michihito Ueda , Kiyoshi Morimoto , Kiyoyuki Morita
发明人： Kenji Toyoda , Michihito Ueda , Kiyoshi Morimoto , Kiyoyuki Morita
IPC分类号： G05F1/10
CPC分类号： G11C11/4087 , G11C11/22 , G11C11/4074
摘要： A voltage generating circuit comprising a capacitor (4), a ferroelectric capacitor (6) serially connected to the capacitor (4), an output terminal (11), a capacitor (10) which grounds the output terminal (11), a supply voltage supplying terminal (13), a switch (1) which connects the supply voltage supplying terminal (13) and the connecting node (N1) of the two capacitors (4, 6), and a switch (9) which connects the connecting node (N1) and output terminal (11); wherein during a first period, with the two switches (1) and (9) placed in the OFF state, a terminal (3) is grounded and a terminal (7) is provided with a supply voltage; wherein during a second period, the terminal (3) is provided with the supply voltage and the switch (9) is placed in the ON state; wherein during a third period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is grounded; wherein during a fourth period, the terminal (7) is provided with the supply voltage; and wherein thereafter the first through fourth periods are repeated.
摘要翻译：一种电压产生电路，包括电容器（4），串联连接到电容器（4）的铁电电容器（6），输出端子（11），接地输出端子（11）的电容器（10）供给端子（13），连接电源电压端子（13）和两个电容器（4,6）的连接节点（N1）的开关（1）和连接节点（N 1）和输出端子（11）; 其中在第一时段期间，当两个开关（1）和（9）处于断开状态时，端子（3）接地，端子（7）被提供有电源电压; 其中在第二时段期间，端子（3）设置有电源电压，开关（9）置于ON状态; 其中，在第三时段期间，开关（9）处于断开状态，开关（1）置于导通状态，端子（7）接地; 其中在第四时段期间，所述端子（7）被提供有电源电压; 此后重复第一至第四周期。

3. 发明授权

US06940740B2 Multilevel semiconductor memory device and method for driving the same as a neuron element in a neural network computer 有权
标题翻译：多电平半导体存储器件及其在神经网络计算机中作为神经元元件驱动的方法
公开(公告)号：US06940740B2
公开(公告)日：2005-09-06
申请号：US10428840
申请日：2003-05-05
申请人： Michihito Ueda , Takashi Ohtsuka , Kiyoyuki Morita
发明人： Michihito Ueda , Takashi Ohtsuka , Kiyoyuki Morita
IPC分类号： G11C11/22 , G11C11/56 , H01L21/8246 , H01L27/105 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11502 , G11C11/22 , G11C11/223 , G11C11/54 , G11C11/5657 , H01L27/105 , H01L27/11507 , H01L29/7881
摘要： A semiconductor device includes: a control-voltage supply unit 110; an MOS transistor including a gate electrode 109 and drain and source regions 103a and 103b; a dielectric capacitor 104; and a resistor 106. The dielectric capacitor 104 and the resistor 106 are disposed in parallel and interposed between the gate electrode 109 and the control-voltage supply unit 110. With this structure, a charge is accumulated in each of an intermediate electrode of the dielectric capacitor 104 and the gate electrode 109 upon the application of a voltage, thereby varying a threshold value of the MOS transistor. In this manner, the history of input signals can be stored as a variation in a drain current in the MOS transistor, thus allowing multilevel information to be held.
摘要翻译：半导体器件包括：控制电压提供单元110; 包括栅电极109和漏极和源极区103a和103b的MOS晶体管; 介质电容器104; 和电阻器106。介质电容器104和电阻器106并联设置并插入在栅电极109和控制电压供给单元110之间。利用这种结构，在施加电压时，介质电容器104和栅电极109的中间电极中的每一个中积累电荷，从而改变MOS晶体管的阈值。以这种方式，可以将输入信号的历史存储为MOS晶体管中的漏极电流的变化，从而允许保持多电平信息。

4. 发明授权

US06809953B2 Potential generating circuit, potential generating device and semiconductor device using the same, and driving method thereof 有权
标题翻译：电位发生电路，电位产生装置及使用其的半导体装置及其驱动方法
公开(公告)号：US06809953B2
公开(公告)日：2004-10-26
申请号：US10440277
申请日：2003-05-16
申请人： Kenji Toyoda , Michihito Ueda , Kiyoshi Morimoto , Kiyoyuki Morita , Toru Iwata , Jun Kajiwara
发明人： Kenji Toyoda , Michihito Ueda , Kiyoshi Morimoto , Kiyoyuki Morita , Toru Iwata , Jun Kajiwara
IPC分类号： G11C1122
CPC分类号： H02M3/07 , H02M3/073
摘要： A potential generating circuit comprises a capacitor (4); a ferroelectric capacitor (6) connected in series to the capacitor (4); an output terminal (11); a capacitor (10) for grounding the output terminal (11); a switch (9) for connecting a connecting node (5) between the two capacitors (4, 6) to the output terminal (11); and a switch (1) for connecting the connecting node (5) to the ground; wherein during a first period, with the switches (1) and (9) placed in the OFF state, a terminal (3) is provided with a positive potential and a terminal (7) is grounded; wherein during a second period following the first period, the terminal (3) is grounded and the switch (9) is placed in the ON state; wherein during a third period following the second period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is provided with a positive potential; wherein during a fourth period following the third period, the terminal (7) is grounded; and wherein the first through fourth periods are repeated.
摘要翻译：电位发生电路包括电容器（4）; 与电容器（4）串联连接的铁电电容器（6）。输出端子（11）; 用于使输出端子（11）接地的电容器（10）; 用于将两个电容器（4,6）之间的连接节点（5）连接到输出端子（11）的开关（9）; 和用于将连接节点（5）连接到地面的开关（1）; 其中在第一时段期间，当开关（1）和（9）处于断开状态时，端子（3）被提供有正电位并且端子（7）接地; 其中在所述第一周期之后的第二时段期间，所述端子（3）接地，并且所述开关（9）处于接通状态; 其中在所述第二时段之后的第三时段期间，所述开关（9）处于断开状态，所述开关（1）处于接通状态，并且所述端子（7）被提供有正电位; 其中在所述第三周期之后的第四周期期间，所述终端（7）接地; 并且其中重复第一至第四周期。

5. 发明授权

US06720586B1 Method of fabricating nitride semiconductor, method of fabricating nitride semiconductor device, nitride semiconductor device, semiconductor light emitting device and method of fabricating the same 有权
标题翻译：氮化物半导体的制造方法，氮化物半导体器件的制造方法，氮化物半导体器件，半导体发光器件及其制造方法
公开(公告)号：US06720586B1
公开(公告)日：2004-04-13
申请号：US09712127
申请日：2000-11-15
申请人： Isao Kidoguchi , Akihiko Ishibashi , Ryoko Miyanaga , Gaku Sugahara , Masakatsu Suzuki , Masahiro Kume , Yuzaburo Ban , Kiyoyuki Morita , Ayumu Tsujimura , Yoshiaki Hasegawa
发明人： Isao Kidoguchi , Akihiko Ishibashi , Ryoko Miyanaga , Gaku Sugahara , Masakatsu Suzuki , Masahiro Kume , Yuzaburo Ban , Kiyoyuki Morita , Ayumu Tsujimura , Yoshiaki Hasegawa
IPC分类号： H01L3300
CPC分类号： H01L33/12 , H01L21/0237 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/02642 , H01L21/0265 , H01L33/007 , H01L33/405 , H01L33/46 , H01S5/2077 , H01S5/2201 , H01S5/32341 , H01S5/4031 , H01S2304/00
摘要： The method of fabricating a nitride semiconductor of this invention includes the steps of forming, on a substrate, a first nitride semiconductor layer of AluGavInwN, wherein 0≦u, v, w ≦1 and u+v+w=1; forming, in an upper portion of the first nitride semiconductor layer, plural convexes extending at intervals along a substrate surface direction; forming a mask film for covering bottoms of recesses formed between the convexes adjacent to each other; and growing, on the first nitride semiconductor layer, a second nitride semiconductor layer of AlxGayInzN, wherein 0≦x, y, z≦1 and x+y+z=1, by using, as a seed crystal, Cplanes corresponding to top faces of the convexes exposed from the mask film.
摘要翻译：制造本发明的氮化物半导体的方法包括以下步骤：在衬底上形成AluGavInwN的第一氮化物半导体层，其中0≤u，v，w <= 1，u + v + w = 1; 在所述第一氮化物半导体层的上部形成沿着基板表面方向间隔地延伸的多个凸部; 形成用于覆盖形成在彼此相邻的凸起之间的凹部的底部的掩模膜; 并且在第一氮化物半导体层上生长Al x Ga y In z N的第二氮化物半导体层，其中0≤x，y，z <= 1和x + y + z = 1，通过使用对应于从掩模膜暴露的凸起的顶面。

6. 发明授权

US06716663B2 Method for removing foreign matter, method for forming film, semiconductor device and film forming apparatus 失效
标题翻译：异物去除方法，薄膜形成方法，半导体装置和成膜装置
公开(公告)号：US06716663B2
公开(公告)日：2004-04-06
申请号：US10230258
申请日：2002-08-29
申请人： Kiyoyuki Morita , Takashi Ohtsuka , Michihito Ueda
发明人： Kiyoyuki Morita , Takashi Ohtsuka , Michihito Ueda
IPC分类号： H01L2100
CPC分类号： H01L29/513 , C23C16/409 , C23C16/4485 , H01L21/28167 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28291 , H01L21/31691 , H01L29/516 , H01L29/517 , H01L29/518
摘要： A semiconductor substrate is placed within a housing. By supplying organometallic complexes and carbon dioxide in a supercritical state into the housing, a BST thin film is formed on a platinum thin film, while at the same time, carbon compounds, which are produced when the BST thin film is formed, are removed. The solubility of carbon compounds in the supercritical carbon dioxide is very high, and yet the viscosity of the supercritical carbon dioxide is low. Accordingly, the carbon compounds are removable efficiently from the BST thin film. An oxide or nitride film may also be formed by performing oxidation or nitriding at a low temperature using water in a supercritical or subcritical state, for example.
摘要翻译：将半导体衬底放置在壳体内。通过将超临界状态的有机金属配合物和二氧化碳供给到壳体中，在铂薄膜上形成BST薄膜，同时除去形成BST薄膜时产生的碳化合物。碳化合物在超临界二氧化碳中的溶解度非常高，而超临界二氧化碳的粘度低。因此，碳化合物可从BST薄膜有效地去除。氧化物或氮化物膜也可以通过使用例如超临界或亚临界状态的水在低温下进行氧化或氮化来形成。

7. 发明授权

US06689311B2 Method and apparatus for manufacturing sinter, method for measuring concentration of plasticizer, evaluation method, and evaluation apparatus 有权
标题翻译：用于制造烧结体的方法和装置，用于测量增塑剂浓度的方法，评估方法和评价装置
公开(公告)号：US06689311B2
公开(公告)日：2004-02-10
申请号：US09986744
申请日：2001-11-09
申请人： Kiyoyuki Morita , Hideyuki Okinaka , Gen Itakura
发明人： Kiyoyuki Morita , Hideyuki Okinaka , Gen Itakura
IPC分类号： B22F310
CPC分类号： H01G9/0029 , B22F3/1025 , B22F2998/00 , B22F2999/00 , C04B35/4682 , C04B35/632 , C04B35/63408 , C04B35/6342 , C04B35/63424 , C04B35/638 , C04B38/0645 , C04B2235/6581 , B22F7/02 , B22F2202/03 , B22F2202/01
摘要： A method for selectively and rapidly extracting/removing a plasticizer from a compact such as a green laminate that is produced at a certain point in the process of manufacturing a multilayer ceramic capacitor. Carbon dioxide is introduced into a pressure chamber in which the green laminate has been placed, and the temperature and the pressure of the pressure chamber are set to 40° C. and 10 MPa, respectively, so that the pressure chamber is filled with a supercritical carbon dioxide. The plasticizer is extracted/removed from the green laminate by using the supercritical carbon dioxide. Then, a de-binder step and a baking step are performed in an ordinary manner. By performing the de-plasticizer process of selectively extracting/removing the plasticizer before the de-binder step, it is possible to suppress the formation of a graphite-like substance even if the temperature is increased rapidly in the subsequent de-binder step and the baking step. Therefore, the manufacturing yield or the performance of the product from will not be reduced.
摘要翻译：一种用于在制造多层陶瓷电容器的过程中在某一点产生的诸如生坯层压体的压块中选择性并快速地提取/除去增塑剂的方法。将二氧化碳引入到其中已经放置了生坯层压体的压力室中，并且压力室的温度和压力分别设定为40℃和10MPa，使得压力室充满超临界二氧化碳。通过使用超临界二氧化碳从生坯层压体中提取/除去增塑剂。然后，以常规方式进行去粘合剂步骤和烘烤步骤。通过在去粘合剂步骤之前进行选择性提取/除去增塑剂的去增塑剂方法，即使在随后的脱粘合剂步骤中温度快速增加，也可以抑制石墨状物质的形成，并且烘烤步骤因此，制造产量或产品性能不会降低。

8. 发明授权

US6015978A Resonance tunnel device 有权
标题翻译：共振隧道装置
公开(公告)号：US6015978A
公开(公告)日：2000-01-18
申请号：US175505
申请日：1998-10-20
申请人： Koichiro Yuki , Kiyoyuki Morita , Kiyoshi Morimoto , Yoshihiko Hirai
发明人： Koichiro Yuki , Kiyoyuki Morita , Kiyoshi Morimoto , Yoshihiko Hirai
IPC分类号： H01L21/306 , H01L21/329 , H01L29/88 , H01L29/06
CPC分类号： H01L29/6609 , H01L21/30608 , H01L29/882 , Y10S438/962
摘要： The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etching the semiconductor layer using the mask pattern to form a semiconductor microstructure extending in a first direction parallel to a surface of the substrate, wherein, in the step of selectively etching the semiconductor layer, an etching rate in a second direction vertical to the first direction and parallel to the surface of the substrate is substantially zero with respect to an etching rate in the first direction, and a width of the semiconductor microstructure is substantially equal to a shortest distance between the first opening and the second opening in the second direction.
摘要翻译：形成本发明的半导体微结构的方法包括以下步骤：在具有半导体层作为其上部的衬底上形成具有第一开口和第二开口的掩模图案; 以及使用所述掩模图案选择性地蚀刻所述半导体层，以形成在平行于所述基板的表面的第一方向上延伸的半导体微结构，其中，在选择性地蚀刻所述半导体层的步骤中，沿垂直于所述基板的第二方向的蚀刻速率第一方向并平行于衬底的表面相对于第一方向上的蚀刻速率基本上为零，并且半导体微结构的宽度基本上等于第一开口和第二开口在第二方向上的最短距离。

9. 发明授权

US5736421A Semiconductor device and associated fabrication method 失效
标题翻译：半导体器件及相关制造方法
公开(公告)号：US5736421A
公开(公告)日：1998-04-07
申请号：US589897
申请日：1996-01-23
申请人： Hiroshi Shimomura , Kiyoyuki Morita , Takashi Nakabayashi , Takashi Uehara , Mitsuo Yasuhira , Mizuki Segawa , Takehiro Hirai
发明人： Hiroshi Shimomura , Kiyoyuki Morita , Takashi Nakabayashi , Takashi Uehara , Mitsuo Yasuhira , Mizuki Segawa , Takehiro Hirai
IPC分类号： H01L21/768 , H01L21/8239 , H01L21/8242 , H01L27/06 , H01L27/105 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10844 , H01L21/768 , H01L21/76895 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L27/10805
摘要： Mounted on a single semiconductor substrate are a DRAM, MOS transistor, resistor, and capacitor. The gate electrode of the DRAM and the gate electrode of the MOS transistor are formed by a common layer (i.e., a first-level poly-Si layer). The storage electrode of the DRAM. the resistor, and the lower electrode of the capacitor are formed by a common layer (i.e., a third-level poly-Si layer). The plate electrode of the DRAM and the upper electrode of the capacitor are formed by a common layer (i.e., a fourth-level poly-Si layer).
摘要翻译：安装在单个半导体衬底上的是DRAM，MOS晶体管，电阻器和电容器。 DRAM的栅电极和MOS晶体管的栅极由公共层（即，一级多晶硅层）形成。 DRAM的存储电极。电容器的电阻器和下电极由公共层（即，第三级多晶硅层）形成。 DRAM的平板电极和电容器的上电极由公共层（即，第四级多晶硅层）形成。

10. 发明授权

US5273914A Method of fabricating a CMOS semiconductor devices 失效
标题翻译：制造CMOS半导体器件的方法
公开(公告)号：US5273914A
公开(公告)日：1993-12-28
申请号：US900743
申请日：1992-06-19
申请人： Akio Miyajima , Keiichi Kagawa , Akihira Shinohara , Kiyoyuki Morita , Takashi Uehara
发明人： Akio Miyajima , Keiichi Kagawa , Akihira Shinohara , Kiyoyuki Morita , Takashi Uehara
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L21/266
CPC分类号： H01L29/6659 , H01L21/823814 , H01L21/823828 , H01L27/0928 , Y10S148/015
摘要： An ion implantation stopper is formed on a gate electrode extending on a substrate. When ions are implanted into the substrate to form an LDD layer or source and drain regions in the substrate, the stopper functions to prevent the gate electrode from being exposed to ion implantation. The prevention of the exposure of the gate electrode to the ion implantation ensures the prevention of channeling in the gate electrode. The invention includes forming a first protective film on the gate of an NMOS, implanting to form LDD region for the NMOS, implanting to form source and drain regions of a PMOS, forming a second protective film on the gate of the NMOS, implanting to form source and drain regions of the NMOS, the first and second protective films prevent the gate electrode of the NMOS from being exposed to ion implantation during the respective implanting steps so that channeling is prevented from occurring in the gate electrode of the NMOS.
摘要翻译：在基板上延伸的栅电极上形成离子注入阻挡层。当将离子注入到衬底中以在衬底中形成LDD层或源极和漏极区域时，阻挡层用于防止栅电极暴露于离子注入。防止栅电极暴露于离子注入确保防止栅电极中的沟道化。本发明包括在NMOS的栅极上形成第一保护膜，注入以形成用于NMOS的LDD区，注入以形成PMOS的源极和漏极区，在NMOS的栅极上形成第二保护膜，以形成源极和漏极区域中，第一和第二保护膜防止NMOS的栅电极在相应的注入步骤期间暴露于离子注入，从而防止在NMOS的栅电极中发生沟道化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式