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1. 发明授权

US09311142B2 Controlling memory access conflict of threads on multi-core processor with set of highest priority processor cores based on a threshold value of issued-instruction efficiency 有权
标题翻译：基于发出指令效率的阈值，控制多核处理器上的线程的内存访问冲突与一组最高优先级的处理器内核
公开(公告)号：US09311142B2
公开(公告)日：2016-04-12
申请号：US13569725
申请日：2012-08-08
申请人： Koichiro Yamashita , Hiromasa Yamauchi , Kiyoshi Miyazaki
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Kiyoshi Miyazaki
IPC分类号： G06F9/50 , G06F9/48 , G06F13/18 , G06F13/26 , G06F13/16 , G06F9/52 , G06F9/445
CPC分类号： G06F3/0629 , G06F3/0604 , G06F3/0673 , G06F9/44552 , G06F9/4881 , G06F9/52 , G06F13/1652 , G06F13/18 , G06F13/26
摘要： A multi-core processor system includes multiple cores and memory accessible from the cores, where a given core is configured to detect among the cores, first cores having a highest execution priority level; identify among the detected first cores, a second core that caused access conflict of the memory; and control a third core that is among the cores, excluding the first cores and the identified second core, the third core being controlled to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.
摘要翻译：多核处理器系统包括多个核心和可从核心访问的存储器，其中给定核心被配置为在核心之间检测具有最高执行优先级的第一核心; 在检测到的第一核心之间识别引起存储器的访问冲突的第二核心; 并且控制在核心之内的第三核心，不包括第一核心和所识别的第二核心，第三核心被控制以在发生访问冲突的间隔期间执行给定的间隔时，不访问存储器的线程。

2. 发明授权

US08548451B2 Information processing system, apparatus, and method 有权
标题翻译：信息处理系统，装置和方法
公开(公告)号：US08548451B2
公开(公告)日：2013-10-01
申请号：US13251388
申请日：2011-10-03
申请人： Koichiro Yamashita , Hiromasa Yamauchi , Takahisa Suzuki , Koji Kurihara , Kiyoshi Miyazaki
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Takahisa Suzuki , Koji Kurihara , Kiyoshi Miyazaki
IPC分类号： H04W4/02
CPC分类号： H04W4/023 , H04W64/00
摘要： An information processing system includes a first apparatus including a position information transmission unit to transmit information on the position of the first apparatus; and a second apparatus including, a position information acquisition unit to acquire a position of the second apparatus; a position information receiving unit to receive the information on the position of the first apparatus; a relative-position information acquisition unit to acquire relative-position information of the second and the first apparatus on the basis of the information on the position of the second and the first apparatus; and a control unit to control a coupling mode of the second and the first apparatus on the basis of the relative-position information.
摘要翻译：信息处理系统包括：第一装置，包括位置信息发送单元，用于发送关于第一装置的位置的信息; 以及第二装置，包括：位置信息获取单元，用于获取所述第二装置的位置; 位置信息接收单元，用于接收关于所述第一装置的位置的信息; 相对位置信息获取单元，基于关于第二和第一装置的位置的信息来获取第二和第一装置的相对位置信息; 以及控制单元，其基于相对位置信息来控制第二和第一装置的耦合模式。

3. 发明授权

US08543993B2 Compiler, compile method, and processor core control method and processor 失效
标题翻译：编译器，编译方法和处理器核心控制方法和处理器
公开(公告)号：US08543993B2
公开(公告)日：2013-09-24
申请号：US12726526
申请日：2010-03-18
申请人： Koichiro Yamashita
发明人： Koichiro Yamashita
IPC分类号： G06F9/45
CPC分类号： G06F8/452 , G06F8/4432 , G06F9/50 , Y02D10/22 , Y02D10/41
摘要： A compiler compiling a source code and is implemented in a plurality of processor cores includes a parallel loop processing detection unit configured to detect from the source code a loop processing code for execution of an internal processing operation for a given number of repeating times, and an independent parallel loop processing code in the internal processing operation performed for each repetition to be concurrently processed, and a dynamic parallel conversion unit configured to generate a control core code for control of the number of repeating times in the parallel loop processing code and a parallel processing code for changing the number of repeating times corresponding to the control from the control core code.
摘要翻译：编译源代码并实现在多个处理器核心中的编译器包括并行循环处理检测单元，其被配置为从源代码检测用于对给定次数的重复次数执行内部处理操作的循环处理代码，以及对每个重复执行的内部处理操作中的独立并行环处理代码进行并行处理;以及动态并行转换单元，被配置为生成用于控制并行循环处理代码中的重复次数的控制核心代码和并行处理用于从控制核心码改变对应于控制的重复次数的代码。

4. 发明申请

US20130013835A1 MULTICORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD 有权
标题翻译：多重处理器系统，计算机产品和控制方法
公开(公告)号：US20130013835A1
公开(公告)日：2013-01-10
申请号：US13614097
申请日：2012-09-13
申请人： Koji KURIHARA , Koichiro Yamashita , Kiyoshi Miyazaki , Hitoshi Ikeda
发明人： Koji KURIHARA , Koichiro Yamashita , Kiyoshi Miyazaki , Hitoshi Ikeda
IPC分类号： G06F13/18
CPC分类号： G06F9/526 , G06F9/5016 , G06F13/1652
摘要： A multicore processor system includes a processor configured to detect any among a switching process and an assignment process of applications in a multicore processor; acquire upon detecting any among the switching process and the assignment process, a priority level concerning execution of each application assigned to each core of the multicore processor and number of accesses of a shared resource shared by the multicore processor; determine an access ratio of an application whose priority level is highest to each of application remaining after excluding the application whose priority level is highest, among the assigned applications, by comparing the number of accesses by each remaining application and the number of accesses by the application whose priority level is highest; notify an arbiter circuit of the determined access ratios; and arbitrate using the arbiter circuit, the access of the shared resource by the multicore processor, based on the access ratios.
摘要翻译：多核处理器系统包括被配置为检测多核处理器中的应用的切换过程和分配过程中的任何一个的处理器; 在检测到切换过程和分配过程中的任何一个时获取关于分配给多核处理器的每个核心的每个应用的执行的优先级以及由多核处理器共享的共享资源的访问次数; 通过比较每个剩余应用程序的访问次数和应用程序的访问次数，在分配的应用程序中排除优先级最高的应用程序之后，优先级最高的应用程序的优先级最高的应用程序的访问比率优先级最高; 通知仲裁电路确定的访问比率; 并且基于访问比率仲裁使用仲裁器电路，由多核处理器访问共享资源。

5. 发明申请

US20130007758A1 MULTI-CORE PROCESSOR SYSTEM, THREAD SWITCHING CONTROL METHOD, AND COMPUTER PRODUCT 审中-公开
标题翻译：多核处理器系统，线程切换控制方法和计算机产品
公开(公告)号：US20130007758A1
公开(公告)日：2013-01-03
申请号：US13614071
申请日：2012-09-13
申请人： Koichiro Yamashita , Hiromasa Yamauchi , Kiyoshi Miyazaki
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Kiyoshi Miyazaki
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/4825 , G06F2209/486
摘要： A multi-core processor system includes a given core configured to switch at a prescribed switching period, threads assigned to the given core; identify whether the given core has switched threads at a period exceeding the prescribed switching period; correct the prescribed switching period into a shorter switching period, based on a difference of an actual switching period at which the threads have been switched by the given core and the prescribed switching period; and set the corrected switching period as the prescribed switching period.
摘要翻译：多核处理器系统包括被配置为在规定的切换周期切换的给定核心，分配给给定核心的线程; 确定给定的核心是否在超过规定的切换周期的时间段内切换了线程; 基于由给定核心切换线程的实际切换周期与规定切换周期之间的差异，将规定的切换周期更正为更短的切换周期; 并将修正的开关周期设定为规定的切换期间。

6. 发明申请

US20130007490A1 MULTICORE PROCESSOR SYSTEM, POWER CONTROL METHOD, AND COMPUTER PRODUCT 审中-公开
标题翻译：多重处理器系统，功率控制方法和计算机产品
公开(公告)号：US20130007490A1
公开(公告)日：2013-01-03
申请号：US13608001
申请日：2012-09-10
申请人： Koichiro Yamashita , Hiromasa Yamauchi , Kiyoshi Miyazaki , Takahisa Suzuki , Koji Kurihara
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Kiyoshi Miyazaki , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F1/32 , G06F15/76
CPC分类号： G06F9/4893 , G06F1/3203 , G06F1/3243 , G06F9/5094 , Y02D10/152 , Y02D10/22 , Y02D10/24
摘要： A multicore processor system having multiple cores, includes processors configured to measure bandwidth of a network; compare the measured bandwidth and a given threshold; determine among the cores and based on an obtained comparison result, a core adjustment number by which the number of cores executing a given process related to data communicated through the network is adjusted; calculate the number of executing cores after adjustment by the core adjustment number and based on the number of cores executing the given process before the adjustment and the determined core adjustment number; specify a core executing the given process among the cores and based on the calculated number of executing cores after the adjustment; and distribute the communicated data to the specified core executing the given process.
摘要翻译：具有多个核心的多核处理器系统包括被配置为测量网络带宽的处理器; 比较测量带宽和给定阈值; 在核心之间确定并且基于获得的比较结果，调整与执行通过网络传送的数据相关的给定处理的核的数量的核心调整数; 通过核心调整号码计算调整后的执行核心数量，并根据在调整前执行给定进程的核心数量和确定的核心调整号码; 在核心之间指定执行给定进程的核心，并且基于在调整之后计算的执行核心数量; 并将传送的数据分发到执行给定进程的指定核心。

7. 发明申请

US20130007439A1 MULTICORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND NOTIFICATION METHOD 有权
标题翻译：多重处理器系统，计算机产品和通知方法
公开(公告)号：US20130007439A1
公开(公告)日：2013-01-03
申请号：US13613605
申请日：2012-09-13
申请人： Koichiro Yamashita , Hiromasa Yamauchi , Kiyoshi Miyazaki
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Kiyoshi Miyazaki
IPC分类号： G06F9/06
CPC分类号： G06F9/4405 , G06F9/441
摘要： A multicore processor system includes a processor configured to detect, among cores that have booted with an old boot program in the multicore processor, a core to which no process is assigned; change upon detecting a core to which no process is assigned, a reference area from a storage area for the old boot program to a storage area for a new boot program; and notify the core to which no process is assigned of a reboot instruction specifying the reference area after the change.
摘要翻译：多核处理器系统包括处理器，其配置成在多核处理器中用旧引导程序引导的核心之间检测不分配进程的核心; 在检测到没有分配处理的核心的情况下，从旧的引导程序的存储区域到用于新的引导程序的存储区域的参考区域; 并且在更改之后通知指定了指定参考区域的重新引导指令没有进程的核心。

8. 发明申请

US20120088485A1 INFORMATION PROCESSING SYSTEM, APPARATUS, AND METHOD 有权
标题翻译：信息处理系统，装置和方法
公开(公告)号：US20120088485A1
公开(公告)日：2012-04-12
申请号：US13251388
申请日：2011-10-03
申请人： Koichiro YAMASHITA , Hiromasa Yamauchi , Takahisa Suzuki , Koji Kurihara , Kiyoshi Miyazaki
发明人： Koichiro YAMASHITA , Hiromasa Yamauchi , Takahisa Suzuki , Koji Kurihara , Kiyoshi Miyazaki
IPC分类号： H04W4/02
CPC分类号： H04W4/023 , H04W64/00
摘要： An information processing system includes a first apparatus including a position information transmission unit to transmit information on the position of the first apparatus; and a second apparatus including, a position information acquisition unit to acquire a position of the second apparatus; a position information receiving unit to receive the information on the position of the first apparatus; a relative-position information acquisition unit to acquire relative-position information of the second and the first apparatus on the basis of the information on the position of the second and the first apparatus; and a control unit to control a coupling mode of the second and the first apparatus on the basis of the relative-position information.
摘要翻译：信息处理系统包括：第一装置，包括位置信息发送单元，用于发送关于第一装置的位置的信息; 以及第二装置，包括：位置信息获取单元，用于获取所述第二装置的位置; 位置信息接收单元，用于接收关于所述第一装置的位置的信息; 相对位置信息获取单元，基于关于第二和第一装置的位置的信息来获取第二和第一装置的相对位置信息; 以及控制单元，其基于相对位置信息来控制第二和第一装置的耦合模式。

9. 发明申请

US20090325016A1 FUEL CELL STACK 有权
标题翻译：燃料电池堆
公开(公告)号：US20090325016A1
公开(公告)日：2009-12-31
申请号：US12374935
申请日：2007-07-25
申请人： Koichiro Yamashita , Junichi Shirahama , Katsuya Matsuoka , Ikuyasu Kato , Kazuo Horibe , Osamu Hamanoi , Takuya Hashimoto , Hideki Kubo , Masahiro Shiozawa , Ryo Akagawa
发明人： Koichiro Yamashita , Junichi Shirahama , Katsuya Matsuoka , Ikuyasu Kato , Kazuo Horibe , Osamu Hamanoi , Takuya Hashimoto , Hideki Kubo , Masahiro Shiozawa , Ryo Akagawa
IPC分类号： H01M8/04
CPC分类号： H01M8/241 , H01M8/0202 , H01M8/0254 , H01M8/0265 , H01M8/0267 , H01M8/04007 , H01M8/04029 , H01M2008/1095
摘要： A fuel cell stack comprises a stack of three or more fuel cells, each having an assembly in which an anode electrode and a cathode electrode are respectively joined to either side of an electrolytic membrane. The anode electrode is provided nearer to one end, in the stack direction of the fuel cell, than the cathode electrode. Temperature regulating parts for regulating the temperature of the anode electrode of one fuel cell of any two adjacent fuel cells and the cathode electrode of the other fuel cell are disposed at a plurality of positions arranged in the stack direction. The provided temperature regulating parts perform temperature regulation so that the heat dissipating capability of the anode electrode is different in the stack direction from that of the cathode electrode.
摘要翻译：燃料电池堆包括三个或更多个燃料电池的堆叠，每个燃料电池具有其中阳极电极和阴极电极分别连接到电解膜的任一侧的组件。阳极电极设置成比阴极电极更靠近燃料电池的堆叠方向的一端。用于调节任意两个相邻燃料电池的一个燃料电池的阳极电极和另一个燃料电池的阴极电极的温度的温度调节部件设置在堆叠方向上排列的多个位置。提供的温度调节部件执行温度调节，使得阳极电极的散热能力在堆叠方向上与阴极电极的散热能力不同。

10. 发明申请

US20090148746A1 FUEL CELL 有权
标题翻译：燃料电池
公开(公告)号：US20090148746A1
公开(公告)日：2009-06-11
申请号：US12084551
申请日：2006-10-18
申请人： Chisato Kato , Koichiro Yamashita
发明人： Chisato Kato , Koichiro Yamashita
IPC分类号： H01M2/00
CPC分类号： H01M8/0258 , H01M8/04074 , H01M8/04156 , H01M8/04223 , H01M8/0662 , H01M8/1004 , H01M8/24 , H01M8/241
摘要： A heat insulating member is sandwiched by a first separator and a second separator. The heat insulating member functions as a heat insulating layer to prevent the temperature decrease of electricity generating cells. A first impurity removal flow path is formed in the space enclosed by the grooves on the surface of the second separator and a partition plate. A second impurity removal flow path is formed in the space enclosed by the grooves on the surface of a third separator and the partition plate. The impurity removal flow paths function as filters to remove the impurities contained in the reaction gases. A terminal functions as a current collecting layer to collect the electricity generated in the electricity generating cells. An end laminated body functions as a heat insulating layer to prevent the temperature decrease of the electricity generating cells, impurity removal layers to remove the impurities contained in the reaction gases and a current collecting layer to collect the electricity generated in the electricity generating cells.
摘要翻译：绝热部件被第一隔板和第二隔板夹持。绝热构件用作绝热层，以防止发电单元的温度降低。在由第二分离器的表面上的凹槽和隔板形成的空间中形成第一杂质去除流路。在由第三分离器和分隔板的表面上的槽包围的空间中形成第二杂质去除流动路径。杂质去除流动路径用作去除反应气体中所含杂质的过滤器。终端用作集电层以收集在发电单元中产生的电力。端层叠体用作隔热层，以防止发电单元的温度降低，杂质去除层以除去反应气体中所含的杂质和集电层，以收集在发电单元中产生的电力。

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