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1. 发明授权

US09361408B2 Memory system including key-value store 有权
标题翻译：内存系统包括键值存储
公开(公告)号：US09361408B2
公开(公告)日：2016-06-07
申请号：US13569605
申请日：2012-08-08
申请人： Takao Marukame , Atsuhiro Kinoshita , Kosuke Tatsumura
发明人： Takao Marukame , Atsuhiro Kinoshita , Kosuke Tatsumura
IPC分类号： G06F17/30 , G06F12/02
CPC分类号： G06F17/30982 , G06F12/0246 , G06F17/30097 , G06F17/3012 , G06F2212/7201
摘要： According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface.
摘要翻译：根据一个实施例，包括密钥值存储的密钥值存储器的存储器系统包括密钥值数据作为一对密钥和对应于该密钥的值，包括接口，存储器块，地址获取电路和控制器。接口接收数据写/读请求或基于键值存储的请求。存储块具有用于存储数据的数据区域和包含键值数据的元数据表。地址获取电路响应于键的输入而获取地址。控制器执行存储器块的数据写/读请求，并将获取的地址输出到存储块，并根据键值存储执行请求。控制器通过接口输出与该键对应的值。

2. 发明申请

US20150014748A1 SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAMMABLE LOGIC DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路，可编程逻辑器件，制造半导体集成电路的方法
公开(公告)号：US20150014748A1
公开(公告)日：2015-01-15
申请号：US14500349
申请日：2014-09-29
申请人： Koichiro ZAITSU , Kosuke TATSUMURA , Mari MATSUMOTO
发明人： Koichiro ZAITSU , Kosuke TATSUMURA , Mari MATSUMOTO
IPC分类号： H01L27/118
CPC分类号： H01L27/11803 , G11C16/04 , G11C16/0441 , G11C16/10 , H01L21/26586 , H01L21/28273 , H01L21/28282 , H01L27/0207 , H01L27/11526 , H01L27/11534 , H01L27/11573 , H01L29/6653 , H01L29/66537 , H01L29/6659 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H03K19/17764 , H03K19/17792
摘要： According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode.
摘要翻译：根据一个实施例，半导体集成电路包括非易失性存储区域，每个包括第一非易失性存储晶体管，第二非易失性存储晶体管和输出线，第一非易失性存储晶体管包括第一源极扩散区，第一漏极扩散区和第一控制栅极，第二非易失性存储晶体管包括第二源极扩散区，第二漏极扩散区和第二控制栅电极，连接第一漏极扩散区域和第二漏极扩散区域的输出线以及逻辑晶体管区域每个都包括逻辑晶体管，逻辑晶体管包括第三源极扩散区，第三漏极扩散区和第一栅电极。

3. 发明申请

US20140035619A1 SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAMMABLE LOGIC DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CITCUIT 有权
标题翻译：半导体集成电路，可编程逻辑器件，制造半导体集成电路的方法
公开(公告)号：US20140035619A1
公开(公告)日：2014-02-06
申请号：US13622015
申请日：2012-09-18
申请人： Koichiro Zaitsu , Kosuke Tatsumura , Mari Matsumoto
发明人： Koichiro Zaitsu , Kosuke Tatsumura , Mari Matsumoto
IPC分类号： G11C11/34 , H01L21/425 , H03K19/177
CPC分类号： H01L27/11803 , G11C16/04 , G11C16/0441 , G11C16/10 , H01L21/26586 , H01L21/28273 , H01L21/28282 , H01L27/0207 , H01L27/11526 , H01L27/11534 , H01L27/11573 , H01L29/6653 , H01L29/66537 , H01L29/6659 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H03K19/17764 , H03K19/17792
摘要： According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode.
摘要翻译：根据一个实施例，半导体集成电路包括非易失性存储区域，每个包括第一非易失性存储晶体管，第二非易失性存储晶体管和输出线，第一非易失性存储晶体管包括第一源极扩散区，第一漏极扩散区和第一控制栅极，第二非易失性存储晶体管包括第二源极扩散区，第二漏极扩散区和第二控制栅电极，连接第一漏极扩散区域和第二漏极扩散区域的输出线以及逻辑晶体管区域每个都包括逻辑晶体管，逻辑晶体管包括第三源极扩散区，第三漏极扩散区和第一栅电极。

4. 发明授权

US08610196B2 Memory including transistors with double floating gate structures 失效
标题翻译：存储器包括具有双浮栅结构的晶体管
公开(公告)号：US08610196B2
公开(公告)日：2013-12-17
申请号：US13608436
申请日：2012-09-10
申请人： Tetsufumi Tanamoto , Kosuke Tatsumura , Kiwamu Sakuma , Atsuhiro Kinoshita , Shinobu Fujita , Koichi Muraoka
发明人： Tetsufumi Tanamoto , Kosuke Tatsumura , Kiwamu Sakuma , Atsuhiro Kinoshita , Shinobu Fujita , Koichi Muraoka
IPC分类号： H01L27/11
CPC分类号： H01L29/42332 , G11C11/412 , G11C14/0063 , H01L27/1104 , H01L29/7881
摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.
摘要翻译：在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极，第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜，第四浮栅，第六绝缘膜和第二控制栅极。

5. 发明授权

US08321421B2 Storage device having full-text search function 有权
标题翻译：存储设备具有全文搜索功能
公开(公告)号：US08321421B2
公开(公告)日：2012-11-27
申请号：US12888897
申请日：2010-09-23
申请人： Kosuke Tatsumura , Atsuhiro Kinoshita
发明人： Kosuke Tatsumura , Atsuhiro Kinoshita
IPC分类号： G06F7/00 , G06F17/00 , G06F17/30
CPC分类号： G06F17/30106 , G06F17/30109
摘要： According to one embodiment, a storage device includes an interface, a first and second memory blocks and a controller. The interface receives a content search request. The first memory block stores files and inverted files corresponding to contents included in the files. The second memory block stores a file search table. The controller creates the inverted file for each content included in the files and stores IDs of the files including the content in the inverted file. The controller obtains, by search of the content, a corresponding inverted file from the inverted files stored in the first memory block and stores, in the file search table, the IDs of the files included in the obtained inverted file. The controller outputs the IDs of the files stored in the file search table from the interface as a search result for the content search request.
摘要翻译：根据一个实施例，存储设备包括接口，第一和第二存储器块以及控制器。接口接收内容搜索请求。第一个存储块存储与文件中包含的内容相对应的文件和反转文件。第二存储器块存储文件搜索表。控制器为包含在文件中的每个内容创建反转文件，并将包含内容的文件的ID存储在反转文件中。控制器通过搜索内容，从存储在第一存储器块中的反转文件中获得相应的反转文件，并在文件搜索表中存储所获得的反转文件中包括的文件的ID。控制器从接口输出存储在文件搜索表中的文件的ID作为内容搜索请求的搜索结果。

6. 发明授权

US09007823B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09007823B2
公开(公告)日：2015-04-14
申请号：US13480853
申请日：2012-05-25
申请人： Takahiro Kurita , Yoshifumi Nishi , Kosuke Tatsumura , Atsuhiro Kinoshita
发明人： Takahiro Kurita , Yoshifumi Nishi , Kosuke Tatsumura , Atsuhiro Kinoshita
IPC分类号： G11C11/34 , H01L21/28 , G11C7/02 , G11C11/403 , H01L29/423 , H01L29/51 , H01L27/108
CPC分类号： H01L21/28291 , G11C7/02 , G11C11/403 , H01L21/28282 , H01L27/108 , H01L27/10873 , H01L29/4234 , H01L29/516
摘要： A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.
摘要翻译：根据实施例的半导体器件包括：第一晶体管，包括连接到第一互连的栅极，第一源极和第一漏极，第一源极和第一漏极中的一个连接到第二互连; 以及第二晶体管，其包括栅极结构，第二源极和第二漏极，所述第二源极和第二漏极中的一个连接到第三互连，并且所述第二源极和第二漏极中的另一个连接到第四互连。栅极结构包括栅极绝缘膜，栅极电极和设置在栅极绝缘膜和栅电极之间以调节阈值电压的阈值调制膜，第一晶体管的第一源极和第一漏极中的另一个被连接到栅电极。

7. 发明授权

US08921920B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08921920B2
公开(公告)日：2014-12-30
申请号：US13418620
申请日：2012-03-13
申请人： Shigeru Kawanaka , Kosuke Tatsumura , Naoki Yasuda , Jun Fujiki , Atsushi Kawasumi
发明人： Shigeru Kawanaka , Kosuke Tatsumura , Naoki Yasuda , Jun Fujiki , Atsushi Kawasumi
IPC分类号： H01L29/792 , H01L21/28 , G11C11/22 , G11C11/412 , G11C14/00 , H01L29/51 , H01L27/11 , H01L27/115 , H01L27/118
CPC分类号： H01L21/28282 , G11C11/22 , G11C11/412 , G11C14/0081 , H01L27/1104 , H01L27/1156 , H01L27/11568 , H01L27/11807 , H01L29/518 , H01L29/792
摘要： A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel.
摘要翻译：半导体器件具有半导体衬底和半导体衬底上具有FET的半导体元件，并且包括根据OFF状态和ON状态的不同阈值电压。半导体元件具有设置在形成半导体基板的沟道的部分上方的绝缘膜，设置在绝缘膜上方的栅电极和设置在绝缘膜和栅电极之间的电荷陷阱膜，并且交换更多的电子栅电极与通道相比。

8. 发明授权

US08908408B2 Circuit having programmable match determination function, and LUT circuit, MUX circuit and FPGA device with such function and method of data writing 有权
标题翻译：具有可编程匹配确定功能的电路，以及具有数据写入功能和方法的LUT电路，MUX电路和FPGA器件
公开(公告)号：US08908408B2
公开(公告)日：2014-12-09
申请号：US13613701
申请日：2012-09-13
申请人： Kosuke Tatsumura , Masato Oda , Atsuhiro Kinoshita , Koichiro Zaitsu , Mari Matsumoto , Shinichi Yasuda
发明人： Kosuke Tatsumura , Masato Oda , Atsuhiro Kinoshita , Koichiro Zaitsu , Mari Matsumoto , Shinichi Yasuda
IPC分类号： G11C15/00
CPC分类号： H03K19/17728 , G11C15/04 , G11C15/046 , H03K19/17712
摘要： A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line.
摘要翻译：根据实施例的电路包括：多个比特串比较器，每个比特串包括多个单比特比较器，每个单比特比较器包括第一和第二输入端，第一和第二匹配确定终端，以及存储数据并反转的存储器成对的数据，第一输入端子连接到相应的搜索线，第二输入端子连接到与相应搜索线配对的反向搜索线，以及匹配线，连接第一和第二匹配确定端子单比特比较器; 其源极连接到电源电压线的预充电晶体管; 连接到预充电晶体管的漏极和位串比较器的匹配线的公共匹配线; 以及输入反相器，其输入连接到公共匹配线。

9. 发明申请

US20140035618A1 CIRCUIT HAVING PROGRAMMABLE MATCH DETERMINATION FUNCTION, AND LUT CIRCUIT, MUX CIRCUIT AND FPGA DEVICE WITH SUCH FUNCTION AND METHOD OF DATA WRITING 有权
标题翻译：具有可编程匹配确定功能的电路，以及具有这种功能的LUT电路，多路复用电路和FPGA器件以及数据写入方法
公开(公告)号：US20140035618A1
公开(公告)日：2014-02-06
申请号：US13613701
申请日：2012-09-13
申请人： Kosuke TATSUMURA , Masato ODA , Atsuhiro KINOSHITA , Koichiro ZAITSU , Mari MATSUMOTO , Shinichi YASUDA
发明人： Kosuke TATSUMURA , Masato ODA , Atsuhiro KINOSHITA , Koichiro ZAITSU , Mari MATSUMOTO , Shinichi YASUDA
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G11C15/04 , G11C15/046 , H03K19/17712
摘要： A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line.
摘要翻译：根据实施例的电路包括：多个比特串比较器，每个比特串包括多个单比特比较器，每个单比特比较器包括第一和第二输入端，第一和第二匹配确定终端，以及存储数据并反转的存储器成对的数据，第一输入端子连接到相应的搜索线，第二输入端子连接到与相应搜索线配对的反向搜索线，以及匹配线，连接第一和第二匹配确定端子单比特比较器; 其源极连接到电源电压线的预充电晶体管; 连接到预充电晶体管的漏极和位串比较器的匹配线的公共匹配线; 以及输入反相器，其输入连接到公共匹配线。

10. 发明申请

US20130241596A1 PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：可编程逻辑器件
公开(公告)号：US20130241596A1
公开(公告)日：2013-09-19
申请号：US13605646
申请日：2012-09-06
申请人： Mari MATSUMOTO , Kosuke Tatsumura , Koichiro Zaitsu
发明人： Mari MATSUMOTO , Kosuke Tatsumura , Koichiro Zaitsu
IPC分类号： H03K19/094
CPC分类号： G11C16/0441 , G11C16/3418 , H03K19/1776
摘要： One embodiment provides a programmable logic device in which a logic switch includes: a first memory having a first terminal connected to a first wire, a second terminal connected to a second wire, and a third terminal connected to a third wire; a second memory having a fourth terminal connected to the first wire, a fifth terminal connected to a fourth wire, and a sixth terminal connected to a fifth wire; and a pass transistor having a gate connected to the first terminal, and a source and a drain respectively connected to a sixth wire and a seventh wire. A source or drain of a first select gate transistor is connected the sixth wire, and a source or drain of a second select gate transistor is connected to the seventh wire.
摘要翻译：一个实施例提供了一种可编程逻辑器件，其中逻辑开关包括：第一存储器，其具有连接到第一线的第一端子，连接到第二线的第二端子和连接到第三线的第三端子; 第二存储器，具有连接到第一线的第四端子，连接到第四线的第五端子和连接到第五线的第六端子; 以及具有连接到第一端子的栅极的通过晶体管，以及分别连接到第六线和第七线的源极和漏极。第一选择栅极晶体管的源极或漏极连接第六导线，第二选择栅极晶体管的源极或漏极连接到第七导线。

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