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1. 发明申请

US20130069134A1 MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES 失效
标题翻译：包含两个浮动门结构的晶体管的存储器
公开(公告)号：US20130069134A1
公开(公告)日：2013-03-21
申请号：US13608436
申请日：2012-09-10
申请人： Tetsufumi TANAMOTO , Kosuke Tatsumura , Kiwamu Sakuma , Atsuhiro Kinoshita , Shinobu Fujita , Koichi Muraoka
发明人： Tetsufumi TANAMOTO , Kosuke Tatsumura , Kiwamu Sakuma , Atsuhiro Kinoshita , Shinobu Fujita , Koichi Muraoka
IPC分类号： H01L27/11
CPC分类号： H01L29/42332 , G11C11/412 , G11C14/0063 , H01L27/1104 , H01L29/7881
摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.
摘要翻译：在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极，第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜，第四浮栅，第六绝缘膜和第二控制栅极。

2. 发明申请

US20120319077A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120319077A1
公开(公告)日：2012-12-20
申请号：US13560557
申请日：2012-07-27
申请人： Naoki YASUDA , Daisuke MATSUSHITA , Koichi MURAOKA
发明人： Naoki YASUDA , Daisuke MATSUSHITA , Koichi MURAOKA
IPC分类号： H01L47/00
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/2418 , H01L27/2481
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of first interconnections arranged parallel, a plurality of second interconnections arranged parallel to intersect the first interconnections, and memory cell portions respectively arranged at intersecting portions between the first and second interconnections and each configured by laminating a variable-resistance element and a diode element. The diode element has a laminated structure having a first insulating film, a conductive fine grain layer and a second insulating film. The physical film thickness of the second insulating film is greater than the first insulating film and the dielectric constant of the second insulating film is greater than the first insulating film.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括平行布置的多个第一互连，并行布置成与第一互连相交的多个第二互连，以及分别布置在第一和第二互连之间的相交部分处的每个配置的存储单元部分通过层叠可变电阻元件和二极管元件。二极管元件具有具有第一绝缘膜，导电细晶粒层和第二绝缘膜的层叠结构。第二绝缘膜的物理膜厚度大于第一绝缘膜，并且第二绝缘膜的介电常数大于第一绝缘膜。

3. 发明申请

US20120193597A1 NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20120193597A1
公开(公告)日：2012-08-02
申请号：US13362832
申请日：2012-01-31
申请人： Masao SHINGU , Akira Takashima , Koichi Muraoka
发明人： Masao SHINGU , Akira Takashima , Koichi Muraoka
IPC分类号： H01L45/00 , H01L27/06 , H01L27/24
CPC分类号： H01L45/1273 , H01L27/101 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/1226 , H01L45/146 , H01L45/1616 , H01L45/1675
摘要： According to one embodiment, a nonvolatile memory device includes a memory section. The memory section includes a first insulating layer, a second insulating layer and a pair of electrodes. The second insulating layer is formed on and in contact with the first insulating layer. The second insulating layer has at least one of a composition different from a composition of the first insulating layer and a phase state different from a phase state of the first insulating layer. The pair of electrodes is capable of passing a current through a current path along a boundary portion between the first insulating layer and the second insulating layer. An electrical resistance of the current path is changed by a voltage applied between the pair of electrodes.
摘要翻译：根据一个实施例，非易失性存储器件包括存储器部分。存储部分包括第一绝缘层，第二绝缘层和一对电极。第二绝缘层形成在第一绝缘层上并与第一绝缘层接触。第二绝缘层具有与第一绝缘层的组成不同的组成和与第一绝缘层的相位状态不同的相位状态中的至少一个。一对电极能够使电流通过沿着第一绝缘层和第二绝缘层之间的边界部分的电流路径。通过施加在该对电极之间的电压来改变电流路径的电阻。

4. 发明申请

US20120139030A1 NONVOLATILE SEMICONDUCTOR MEMORY 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20120139030A1
公开(公告)日：2012-06-07
申请号：US13316603
申请日：2011-12-12
申请人： Kiwamu SAKUMA , Atsuhiro Kinoshita , Masahiro Kiyotoshi , Daisuke Hagishima , Koichi Muraoka
发明人： Kiwamu SAKUMA , Atsuhiro Kinoshita , Masahiro Kiyotoshi , Daisuke Hagishima , Koichi Muraoka
IPC分类号： H01L27/105 , H01L21/8239
CPC分类号： H01L29/42328 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.
摘要翻译：根据一个实施例，非易失性半导体存储器包括在第一方向上的第一至第n（n是不小于2的自然数）半导体层，并且在第二方向上延伸，并且半导体层具有阶梯状图案第二方向的第一端，在第二方向的第一端中共同连接到第一至第n半导体层的公共半导体层，第一至第n层选择晶体管，其从第一电极侧第一电极和第一至第n存储器串以及使第i层选择晶体管（i为1至n之一）的第一至第n杂质区在第一端中的正常导通状态第i个半导体层的第2方向。

5. 发明申请

US20120025297A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120025297A1
公开(公告)日：2012-02-02
申请号：US13204412
申请日：2011-08-05
申请人： Akira TAKASHIMA , Masao SHINGU , Koichi MURAOKA
发明人： Akira TAKASHIMA , Masao SHINGU , Koichi MURAOKA
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L21/02145 , H01L21/02156 , H01L21/02161 , H01L21/28273 , H01L27/11521 , H01L27/11568 , H01L29/4234 , H01L29/513
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a source region and a drain region provided on a surface area of a semiconductor region, a tunnel insulating film provided on a channel between the source region and the drain region, a charge storage layer provided on the tunnel insulating film, a first dielectric film provided on the charge storage layer and containing lanthanum aluminum silicon oxide or oxynitride, a second dielectric film provided on the first dielectric film and containing oxide or oxynitride containing at least one of hafnium (Hf), zirconium (Zr), titanium (Ti), and a rare earth metal, and a control gate electrode provided on the second dielectric film.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括设置在半导体区域的表面区域上的源极区域和漏极区域，设置在源极区域和漏极区域之间的沟道上的隧道绝缘膜，设置有电荷存储层在隧道绝缘膜上，设置在电荷存储层上并含有镧铝氧化物或氧氮化物的第一电介质膜，设置在第一电介质膜上并含有氧化物或氮氧化物的第二电介质膜，其含有铪（Hf），锆（Zr），钛（Ti）和稀土金属，以及设置在第二电介质膜上的控制栅电极。

6. 发明授权

US08058681B2 Nonvolatile semiconductor memory element, nonvolatile semiconductor memory, and method for operating nonvolatile semiconductor memory element 有权
标题翻译：非易失性半导体存储元件，非易失性半导体存储器以及用于操作非易失性半导体存储元件
公开(公告)号：US08058681B2
公开(公告)日：2011-11-15
申请号：US12405626
申请日：2009-03-17
申请人： Masao Shingu , Jun Fujiki , Naoki Yasuda , Koichi Muraoka
发明人： Masao Shingu , Jun Fujiki , Naoki Yasuda , Koichi Muraoka
IPC分类号： H01L29/792
CPC分类号： H01L29/7883 , G11C11/40 , G11C16/0408 , G11C16/0466 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , H01L21/28282 , H01L27/11521 , H01L27/11556 , H01L27/11582 , H01L29/4234 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/788 , H01L29/792
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
摘要翻译：根据本发明的一个方面，提供了一种非易失性半导体存储元件，包括：半导体衬底，包括：源极区; 漏区; 和通道区域; 形成在沟道区上的下绝缘膜; 电荷存储膜，形成在下绝缘膜上并存储数据; 形成在电荷存储膜上的上绝缘膜; 以及形成在所述上绝缘膜上的控制栅极，其中所述上绝缘膜包括：第一绝缘膜; 以及与所述第一绝缘膜层压的第二绝缘膜，并且其中所述第一绝缘膜形成为具有比所述第二绝缘膜的陷阱级密度大的陷阱级密度。

7. 发明授权

US07999303B2 NAND-type nonvolatile semiconductor memory device 有权
标题翻译： NAND型非易失性半导体存储器件
公开(公告)号：US07999303B2
公开(公告)日：2011-08-16
申请号：US12353586
申请日：2009-01-14
申请人： Shoko Kikuchi , Yasushi Nakasaki , Koichi Muraoka
发明人： Shoko Kikuchi , Yasushi Nakasaki , Koichi Muraoka
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/78
摘要： The present invention provides a high-performance MONOS-type NAND-type nonvolatile semiconductor memory device using an aluminum oxide film as a part of gate insulating film in a select transistor and as a block insulating film in a memory transistor. The NAND-type nonvolatile semiconductor memory device has, on a semiconductor substrate, a plurality of memory cell transistors connected to each other in series and a select transistor. The memory cell transistor includes a first insulating film on the semiconductor substrate, a charge trapping layer, a second insulating film made of aluminum oxide,a first control gate electrode, and a first source/drain region. The select transistor includes a third insulating film on the semiconductor substrate, a fourth insulating film made of an aluminum oxide containing at least one of a tetravalent cationic element, a pentavalent cationic element, and N (nitrogen), a second control gate electrode, and a second source/drain region.
摘要翻译：本发明提供一种在选择晶体管中使用氧化铝膜作为栅绝缘膜的一部分的高性能MONOS型NAND型非易失性半导体存储器件，并且作为存储晶体管中的块绝缘膜。 NAND型非易失性半导体存储器件在半导体衬底上具有串联连接的多个存储单元晶体管和选择晶体管。存储单元晶体管包括半导体衬底上的第一绝缘膜，电荷俘获层，由氧化铝制成的第二绝缘膜，第一控制栅极电极和第一源极/漏极区域。选择晶体管包括半导体衬底上的第三绝缘膜，由包含四价阳离子元素，五价阳离子元素和N（氮）中的至少一种的氧化铝制成的第四绝缘膜，第二控制栅电极和第二源极/漏极区域。

8. 发明授权

US07943981B2 Semiconductor memory element 有权
标题翻译：半导体存储元件
公开(公告)号：US07943981B2
公开(公告)日：2011-05-17
申请号：US12233073
申请日：2008-09-18
申请人： Tsunehiro Ino , Naoki Yasuda , Koichi Muraoka , Jun Fujiki , Shoko Kikuchi , Keiko Ariyoshi
发明人： Tsunehiro Ino , Naoki Yasuda , Koichi Muraoka , Jun Fujiki , Shoko Kikuchi , Keiko Ariyoshi
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L29/42348 , H01L29/513 , H01L29/518
摘要： A semiconductor memory element includes: a tunnel insulating film formed on a semiconductor substrate; a HfON charge storage film with Bevan clusters formed on the tunnel insulating film; a blocking film formed on the HfON charge storage film; and a gate electrode formed on the blocking film.
摘要翻译：半导体存储元件包括：形成在半导体衬底上的隧道绝缘膜; 在隧道绝缘膜上形成具有Bevan簇的HfON电荷存储膜; 形成在HfON电荷存储膜上的阻挡膜; 以及形成在阻挡膜上的栅电极。

9. 发明授权

US07825458B2 Nonvolatile semiconductor memory and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07825458B2
公开(公告)日：2010-11-02
申请号：US12050427
申请日：2008-03-18
申请人： Tatsuo Shimizu , Koichi Muraoka , Masato Koyama , Shoko Kikuchi
发明人： Tatsuo Shimizu , Koichi Muraoka , Masato Koyama , Shoko Kikuchi
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/66833 , H01L29/785
摘要： A nonvolatile semiconductor memory includes a source area and a drain area provided on a semiconductor substrate with a gap which serves as a channel area, a first insulating layer, a charge accumulating layer, a second insulating layer (block layer) and a control electrode, formed successively on the channel area, and the second insulating layer is formed by adding an appropriate amount of high valence substance into base material composed of substance having a sufficiently higher dielectric constant than the first insulating layer so as to accumulate a large amount of negative charges in the block layer by localized state capable of trapping electrons, so that the high dielectric constant of the block layer and the high electronic barrier are achieved at the same time.
摘要翻译：非易失性半导体存储器包括设置在具有用作沟道区的间隙的半导体衬底上的源区和漏区，第一绝缘层，电荷累积层，第二绝缘层（阻挡层）和控制电极，在通道区域上依次形成，并且通过向具有比第一绝缘层高的介电常数的物质构成的基材中添加适量的高价态物质形成第二绝缘层，以便积累大量的负电荷在阻挡层中通过能够捕获电子的局部状态，从而同时实现阻挡层和高电子势垒的高介电常数。

10. 发明授权

US07816215B2 Semiconductor device manufacturing method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US07816215B2
公开(公告)日：2010-10-19
申请号：US10941814
申请日：2004-09-16
申请人： Daisuke Matsushita , Koichi Muraoka , Seiji Inumiya , Koichi Kato , Kazuhiro Eguchi , Mariko Takayanagi , Yasushi Nakasaki
发明人： Daisuke Matsushita , Koichi Muraoka , Seiji Inumiya , Koichi Kato , Kazuhiro Eguchi , Mariko Takayanagi , Yasushi Nakasaki
IPC分类号： H01L21/336
CPC分类号： H01L21/28202 , H01L21/022 , H01L21/02329 , H01L21/0234 , H01L21/3144 , H01L29/513 , H01L29/518
摘要： A semiconductor device manufacturing method comprises: forming a gate insulative film on a semiconductor substrate by: forming a first nitride film on the substrate; forming a first oxide film and a second oxide film, the first oxide film being between the substrate and the first nitride film, the second oxide film being on the first nitride film; and nitriding the second oxide film to form, on the first nitride film, one of either: a second nitride film or an SiON film; and forming a gate electrode on the gate insulative film; wherein the equivalent oxide thickness of the gate insulative film is equal to or less than 1 nm.
摘要翻译：一种半导体器件制造方法，包括：在半导体衬底上形成栅极绝缘膜，方法是在衬底上形成第一氮化物膜; 形成第一氧化物膜和第二氧化物膜，所述第一氧化膜位于所述衬底和所述第一氮化物膜之间，所述第二氧化物膜位于所述第一氮化物膜上; 并且对所述第二氧化物膜进行氮化以在所述第一氮化物膜上形成以下之一：第二氮化物膜或SiON膜; 并在所述栅极绝缘膜上形成栅电极; 其中所述栅绝缘膜的等效氧化物厚度等于或小于1nm。

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